74HC4020D,653

74HC4020 74HCT4020 14-stage binary ripple counter Rev. 8 7 September 2021 Product data sheet 1. General description The 74HC4020 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC4020: CMOS level For 74HCT4020: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Applications Frequency dividing circuits Time delay circuits Control countersNexperia 74HC4020 74HCT4020 14-stage binary ripple counter 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4020D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT4020D 74HC4020PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT4020PW 74HC4020BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT4020BQ body 2.5 3.5 0.85 mm 5. Functional diagram 10 CP T 14-STAGE COUNTER 11 MR C D 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aal201 Fig. 1. Functional diagram CTR14 + Q0 9 10 0 9 Q3 7 11 CT = 0 7 Q4 5 5 Q5 4 4 10 CP Q6 6 6 Q7 13 13 CT Q8 12 12 Q9 14 14 11 MR Q10 15 15 Q11 1 1 Q12 2 2 Q13 3 13 3 001aal202 001aal203 Fig. 2. Logic symbol Fig. 3. IEC logic symbol Q Q Q Q Q FF FF FF FF FF CP T 1 T 2 T 3 T 4 T 6 Q Q Q Q Q RD RD RD RD RD MR Q0 Q3 Q13 001aal204 Fig. 4. Logic diagram 74HC HCT4020 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 7 September 2021 2 / 16