Product Information

74LVT573D,112

74LVT573D,112 electronic component of Nexperia

Datasheet
Latches 3.3V OCTAL D TRANS
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

3040: USD 0.2477 ea
Line Total: USD 753.01

0 - Global Stock
MOQ: 3040  Multiples: 1520
Pack Size: 1520

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Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 3040
Multiples : 1520

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74LVT573D,112
Nexperia

3040 : USD 0.2477
6080 : USD 0.2348
9120 : USD 0.2308
15200 : USD 0.2247
30400 : USD 0.2227

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Type
Logic Family
Polarity
Quiescent Current
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Package / Case
Packaging
Function
Height
Length
Output Type
Type
Width
Brand
Mounting Style
Number Of Channels
Number Of Input Lines
Supply Current - Max
Operating Supply Voltage
Reset Type
Factory Pack Quantity :
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Additional Infomation About Product

74LVT573 3.3 V octal D-type transparent latch 3-state Rev. 8 22 November 2011 Product data sheet 1. General description The 74LVT573 is a high-performance BiCMOS product designed for V operation at CC 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE) input is High. The latch remains transparent to the data inputs while LE is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-state buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance OFF state, which means they will neither drive nor load the bus. 2. Features and benefits Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection JESD78 class II exceeds 500 mA ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C74LVT573 Nexperia 3.3 V octal D-type transparent latch 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT573D 40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LVT573DB 40 C to +85 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LVT573PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74LVT573BQ 40 Cto+85 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 C1 1 EN1 1 2 19 1D OE 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 7 14 D5 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 LE mna807 11 mna808 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVT573 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 8 22 November 2011 2 of 17

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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