NBSG14MNG ON Semiconductor

NBSG14 2.5 V/3.3 VSiGe Differential 1:4 Clock/Data Driver with RSECL* Outputs *Reduced Swing ECL NBSG14 V Q0 Q0 V EE CC Exposed Pad (EP) 16 15 14 13 VTCLK 1 12 Q1 CLK 2 11 Q1 NBSG14 CLK 3 10 Q2 VTCLK 4 9 Q2 56 7 8 V Q3 Q3 V EE CC Figure 1. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTCLK Internal 50 Termination pin. See Table 2. 2 CLK ECL, CML, Inverted Differential Input. Internal 75 k to V and 36.5 k to V . EE CC LVCMOS, LVDS, LVTTL Input 3 CLK ECL, CML, Noninverted Differential Input. Internal 75 k to VEE. LVCMOS, LVDS, LVTTL Input 4 VTCLK Internal 50 Termination Pin. See Table 2. 5, 16 V Negative Supply Voltage. All V Pins must be Externally Connected to Power Supply to EE EE Guarantee Proper Operation. 6 Q3 RSECL Output Inverted Differential Output 3. Typically Terminated with 50 to V = V 2 V TT CC 7 Q3 RSECL Output Noninverted Differential Output 3. Typically Terminated with 50 to V = V 2 V TT CC 8, 13 V Positive Supply Voltage. All V Pins must be Externally Connected to Power Supply to CC CC Guarantee Proper Operation. 9 Q2 RSECL Output Inverted Differential Output 2. Typically Terminated with 50 to V = V 2 V TT CC 10 Q2 RSECL Output Noninverted Differential Output 2. Typically Terminated with 50 to V = V 2 V TT CC 11 Q1 RSECL Output Inverted Differential Output 1. Typically Terminated with 50 to V = V 2 V TT CC 12 Q1 RSECL Output Noninverted Differential Output 1. Typically Terminated with 50 to V = V 2 V TT CC 14 Q0 RSECL Output Inverted Differential Output 0. Typically Terminated with 50 to V = V 2 V TT CC 15 Q0 RSECL Output Noninverted Differential Output 0. Typically Terminated with 50 to V = V 2 V TT CC EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no signal is applied then the device will be susceptible to self-oscillation.