DATA SHEET www.onsemi.com 2 MHz Non-Synchronous 8 SEPIC/Boost Controller 1 SOIC8 D SUFFIX NCV898031 CASE 751 The NCV898031 is an adjustable output nonsynchronous 2 MHz SEPIC/boost controller which drives an external N channel MARKINGDIAGRAM MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that 8 supplies charge to the gate driver. 898031G Protection features include internallyset softstart, undervoltage ALYW lockout, cyclebycycle current limiting and thermal shutdown. Additional features include low quiescent current sleep mode and 1 microprocessor compatible enable pin. 898031G = Specific Device Code Features A = Assembly Location Peak Current Mode Control with Internal Slope Compensation L = Wafer Lot 1.2 V 2% Reference Voltage Y = Year W = Work Week 2 MHz Fixed Frequency Operation = PbFree Package Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump Input Undervoltage Lockout (UVLO) PIN CONNECTIONS Internal SoftStart Low Quiescent Current in Sleep Mode (< 10 A Typical) 1 8 EN VFB CyclebyCycle Current Limit Protection 2 ISNS 7 VC HiccupMode Overcurrent Protection (OCP) 3 GND 6 VIN HiccupMode ShortCircuit Protection (SCP) Thermal Shutdown (TSD) 4 GDRV 5 VDRV NCV Prefix for Automotive and Other Applications Requiring (Top View) Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable This is a PbFree Device ORDERING INFORMATION Typical Applications Device Package Shipping Small Form Factor PointofLoad Power Regulation NCV898031D1R2G SOIC8 2500 / Tape & Headlamps (PbFree) Reel Backlighting For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2021 Rev. 17 NCV898031/DNCV898031 V g VIN 6 C TEMP g L1 VDRV ENABLE C DRV C CPL FAULT D 1 VDRV LOGIC 5 Q EN V o CLK OSC DRIVE GDRV 4 L2 LOGIC SC ISNS C o 2 CL CSA R SNS GND VC 3 7 + SCP R F1 R C VFB 8 Gm C C R F2 SS V ref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin Symbol Pin No. Function 1 EN Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enable timeout period. 2 ISNS Current sense input. Connect this pin to the source of the external NMOSFET, through a currentsense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. 5 VDRV Driving voltage. Internally regulated supply for driving the external N MOSFET, sourced from VIN. Bypass with a 1.0 F ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi- tion to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. www.onsemi.com 2 PWN