256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs IDT71V65603 ZBT Feature IDT71V65803 3.3V I/O, Burst Counter Pipelined Outputs Features Address and control signals are applied to the SRAM during one clock 256K x 36, 512K x 18 memory configurations cycle, and two cycles later the associated data cycle occurs, be it read or write. Supports high performance system speed - 150MHz The IDT71V65603/5803 contain data I/O, address and control signal (3.8ns Clock-to-Data Access) registers. Output enable is the only asynchronous signal and can be used TM ZBT Feature - No dead cycles between write and read cycles to disable the outputs at any given time. Internally synchronized output buffer enable eliminates the A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803 to need to control OEOEOEOEOE be suspended as long as necessary. All synchronous inputs are ignored when Single R/WWWWW (READ/WRITE) control pin (CEN) is high and the internal device registers will hold their previous values. Positive clock-edge triggered address, data, and control There are three chip enable pins (CE1, CE2, CE2) that allow the user signal registers for fully pipelined applications to deselect the device when desired. If any one of these three are not asserted 4-word burst capability (interleaved or linear) when ADV/LD is low, no new memory operation can be initiated. However, Individual byte write (BWBWBWBWBW1 - BWBWBWBWBW4) control (May tie active) any pending data transfers (reads or writes) will be completed. The data bus Three chip enables for simple depth expansion will tri-state two cycles after chip is deselected or a write is initiated. 3.3V power supply (5%) The IDT71V65603/5803 have an on-chip burst counter. In the burst 3.3V I/O Supply (VDDQ) mode, the IDT71V65603/5803 can provide four cycles of data for a single Power down controlled by ZZ input address presented to the SRAM. The order of the burst sequence is Packaged in a JEDEC standard 100-pin plastic thin quad defined by the LBO input pin. The LBO pin selects between linear and flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch interleaved burst sequence. The ADV/LD signal is used to load a new ball grid array(fBGA). external address (ADV/LD = LOW) or increment the internal burst counter Description (ADV/LD = HIGH). The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit The IDT71V65603/5803 SRAM utilize IDT s latest high-performance (9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100- cycles when turning the bus around between reads and writes, or writes and pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and TM reads. Thus, they have been given the name ZBT , or Zero Bus Turnaround. 165 fine pitch ball grid array (fBGA) . Pin Description Summary A0-A18 Address Inputs Input Synchronous CE , CE , CE Chip Enables Input Synchronous 1 2 2 Output Enable Input Asynchronous OE R/W Read/Write Signal Input Synchronous Clock Enable Input Synchronous CEN BW , BW , BW , BW Individual Byte Write Selects Input Synchronous 1 2 3 4 CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous Linear / Interleaved Burst Order Input Static LBO ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5304 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc. SEPTEMBER 2004 1 2004 Integrated Device Technology, Inc. DSC-5304/06IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges (1) Pin Definitions Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. Individual Byte I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. BW1-BW4 Write Enables On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW -BW ) must be valid. The byte write signal must also be valid on each cycle of 1 4 a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. CE CE Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the 1, 2 IDT71V65603/5803. (CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the TM rising edge of clock, initiates a deselect cycle. The ZBT has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. CE2 Chip Enable I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71V65603/5803. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are I/OP1-I/OP4 registered and triggered by the rising edge of CLK. LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V65603/5803. When OE is high the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. ZZ Sleep Mode I N/A Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the 71V65603/5803 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. 5304tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.422