SINGLE CHANNEL E1 SHORT IDT82V2051E HAUL LINE INTERFACE UNIT FEATURES Single channel E1 short haul line interfaces - High impedance setting for line drivers Supports HPS (Hitless Protection Switching) for 1+1 protection - PRBS (Pseudo Random Bit Sequence) generation and detection 15 without external relays with 2 -1 PRBS polynomials Single 3.3 V power supply with 5 V tolerance on digital interfaces - 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS error Meets or exceeds specifications in counter - ANSI T1.102 - Analog loopback, Digital loopback, Remote loopback - ITU I.431, G.703, G.736, G.775 and G.823 Short circuit protection and internal protection diode for line - ETSI 300-166, 300-233 and TBR12/13 drivers Software programmable or hardware selectable on: AIS (Alarm Indication Signal) detection - Wave-shaping templates Supports serial control interface, Motorola and Intel Multiplexed - Line terminating impedance (75 /120 ) interfaces and hardware control mode - Adjustment of arbitrary pulse shape Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU - JA (Jitter Attenuator) position (receive path or transmit path) and 82V2041E T1/E1/J1 Short Haul LIU - Single rail/dual rail system interfaces Package: - HDB3/AMI line encoding/decoding Available in 44-pin TQFP packages - Active edge of transmit clock (TCLK) and receive clock (RCLK) Green package options available - Active level of transmit data (TDATA) and receive data (RDATA) - Receiver or transmitter power down DESCRIPTION The IDT82V2051E is a single channel E1 Line Interface Unit. The circuit is integrated in the chip, and different types of loopbacks can be set IDT82V2051E performs clock/data recovery, AMI/HDB3 line decoding and according to the applications. Two different kinds of line terminating imped- detects and reports the LOS conditions. An integrated Adaptive Equalizer ance, 75 and 120 are selectable. The chip also provides driver short- is available to increase the receive sensitivity and enable programming of circuit protection and internal protection diode. The chip can be controlled LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform by either software or hardware. Shaper. There is one Jitter Attenuator, which can be placed in either the The IDT82V2051E can be used in LAN, WAN, Routers, Wireless Base receive path or the transmit path. The Jitter Attenuator can also be disabled. Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, The IDT82V2051E supports both Single Rail and Dual Rail system inter- CSU/DSU equipment, etc. faces. To facilitate the network maintenance, a PRBS generation/detection IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 December 9, 2005 DSC-6528/2IDT82V2051E SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM LOS/AIS LOS Detector Receiver RCLK Data and Adaptive RTIP Data Jitter HDB3/AMI Internal RD/RDP Clock Equalizer Slicer Attenuator Decoder Termination Recovery RRING CV/RDN PRBS Detector Analog Remote Digital Loopback Loopback Loopback TCLK TTIP Transmitter Jitter Line Waveform HDB3/AMI TD/TDP Internal Attenuator Driver Shaper TRING Decoder TDN Termination PRBS Generator TAOS Clock Register Software Control Interface Pin Control Generator Files VDDIO VDDD VDDA VDDT Figure-1 Block Diagram Functional Block Diagram 2 December 9, 2005 MCLK INT CS SDO / ACK / RDY SCLK/ALE/AS RD / DS / SCLKE SDI/ WR /R/W AD 7:0 MODE 1:0 TERM RXTXM 1:0 PULS PATT 1:0 JA 1:0 MONT LP 1:0 THZ RCLKE RPD RST