Product Information

82V2084PFG

82V2084PFG electronic component of Renesas

Datasheet
Telecom Interface ICs QUAD LH LIU

Manufacturer: Renesas
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Price (USD)

1: USD 85.5178 ea
Line Total: USD 85.5178

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1
Multiples : 1

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82V2084PFG
Renesas

1 : USD 85.5178
10 : USD 74.3794
30 : USD 71.9696

0 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 105
Multiples : 105

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82V2084PFG
Renesas

105 : USD 64.7862

0 - Global Stock


Ships to you between Thu. 11 Apr to Mon. 15 Apr

MOQ : 1
Multiples : 1

Stock Image

82V2084PFG
Renesas

1 : USD 71.5898
10 : USD 65.2719
30 : USD 63.1551

     
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QUAD CHANNEL T1/E1/J1 LONG HAUL/ IDT82V2084 SHORT HAUL LINE INTERFACE UNIT FEATURES: Four channel T1/E1/J1 long haul/short haul line interfaces - Active level of transmit data (TDATA) and receive data (RDATA) Supports HPS (Hitless Protection Switching) for 1+1 protection - Receiver or transmitter power down without external relays - High impedance setting for line drivers Receiver sensitivity exceeds -36 dB 772KHz and -43 dB 1024 - PRBS (Pseudo Random Bit Sequence) generation and detection 15 KHz with 2 -1 PRBS polynomials for E1 Programmable T1/E1/J1 switchability allowing one bill of ma- - QRSS (Quasi Random Sequence Signals) generation and detection terial for any line condition 20 with 2 -1 QRSS polynomials for T1/J1 Single 3.3 V power supply with 5 V tolerance on digital interfaces - 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS Meets or exceeds specifications in error counter - ANSI T1.102, T1.403 and T1.408 - Analog loopback, Digital loopback, Remote loopback and Inband - ITU I.431, G.703,G.736, G.775 and G.823 loopback - ETSI 300-166, 300-233 and TBR 12/13 Per channel cable attenuation indication - AT&T Pub 62411 Adaptive receive sensitivity Per channel software selectable on: Non-intrusive monitoring per ITU G.772 specification - Wave-shaping templates for short haul and long haul LBO (Line Build Short circuit protection for line drivers Out) LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection - Line terminating impedance (T1:100 , J1:110 , E1:75 /120 ) JTAG interface - Adjustment of arbitrary pulse shape Supports serial control interface, Motorola and Intel Non-Multi- - JA (Jitter Attenuator) position (receive path or transmit path) plexed interfaces - Single rail/dual rail system interfaces Package: - B8ZS/HDB3/AMI line encoding/decoding IDT82V2084: 128-pin TQFP - Active edge of transmit clock (TCLK) and receive clock (RCLK) DESCRIPTION: The IDT82V2084 can be configured as a quad T1, quad E1 or quad J1 both serial and parallel control interfaces. To facilitate the network mainte- Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to nance, a PRBS/QRSS generation/detection circuit is integrated in each remove the distortion introduced by the cable attenuation. The IDT82V2084 channel, and different types of loopbacks can be set on a per channel basis. also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and Four different kinds of line terminating impedance, 75, 100 , 110 and detects and reports the LOS conditions. In transmit path, there is an AMI/ 120 are selectable on a per channel basis. The chip also provides driver B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter short-circuit protection and supports JTAG boundary scanning. Attenuator for each channel, which can be placed in either the receive path The IDT82V2084 can be used in SDH/SONET, LAN, WAN, Routers, or the transmit path. The Jitter Attenuator can also be disabled. The Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay IDT82V2084 supports both Single Rail and Dual Rail system interfaces and Access Devices, CSU/DSU equipment, etc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGES February 11, 2009 1 2003 Integrated Device Technology, Inc. All rights reserved. DSC-6221/5INDUSTRIAL QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM TDO TDI TMS TCK TRST RST REF THZ SCLKE INT/MOT P/S A 7:0 D 7:0 INT SDO SDI/R/W/WR DS/RD SCLK CS MCLKS MCLK Figure-1 Block Diagram 2 One of the Four Identical Channels LOS/AIS LOSn Detector Receiver RCLKn B8ZS/ Clock and RTIPn Jitter Data Adaptive RDn/RDPn Internal HDB3/AMI Data Attenuator Slicer Equalizer Termination RRINGn CVn/RDNn Decoder Recovery PRBS Detector Analog Digital Remote IBLC Detector Loopback Loopback Loopback B8ZS/ TTIPn TCLKn Transmitter Jitter Waveform Line TDn/TDPn HDB3/AMI Internal Attenuator Shaper/LBO Driver Encoder TRINGn TDNn Termination PRBS Generator IBLC Generator TAOS VDDD Microprocessor G.772 Clock Basic JTAG TAP VDDIO Interface Monitor Generator Control VDDA VDDT VDDR

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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