82C88
Data Sheet August 25, 2005 FN2979.2
CMOS Bus Controller Features
The Intersil 82C88 is a high performance CMOS Bus
Compatible with Bipolar 8288
Controller manufactured using a self-aligned silicon gate
Performance Compatible with:
CMOS process (Scaled SAJI IV). The 82C88 provides the
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
control and command timing signals for 80C86, 80C88,
- 80186/80188. . . . . . . . . . . . . . . . . . . . . . . . . . (6/8MHz)
8086, 8088, 8089, 80186, and 80188 based systems. The
- 8086/8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
high output drive capability of the 82C88 eliminates the need
-8089
for additional bus drivers.
Provides Advanced Commands for Multi-Master Busses
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
Three-State Command Outputs
to or greater than existing equivalent products at a significant
Bipolar Drive Capability
power savings.
Scaled SAJI IV CMOS Process
Pinouts
Single 5V Power Supply
20 LD PDIP, CERDIP
Low Power Operation
TOP VIEW
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10A (Max)
1 20 - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)
IOB V
CC
2
CLK 19 Operating Temperature Ranges
S0
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
S1 3 18
S2
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
DT/ R 4 17
MCE/PDEN
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C
ALE 5 16
DEN
Pb-Free Plus Anneal Available (RoHS Compliant)
AEN 6 15
CEN
Ordering Information
7 14
MRDC INTA
TEMP
8 13
AMWC IORC
PART PART RANGE PKG.
NUMBER MARKING PACKAGE (C) DWG. #
9 12
MWTC
AIOWC
CP82C88 CP82C88 20 Ld PDIP 0 to +70 E20.3
GND 10 11
IOWC
CP82C88Z CP82C88Z 20 Ld PDIP 0 to +70 E20.3
(Note) (Pb-free)
20 LD PLCC, CLCC
TOP VIEW
CP82C88-10 CP82C88-10 20 Ld PDIP 0 to +70 E20.3
IP82C88 IP82C88 -40 to +85 E20.3
CS82C88 CS82C88 20 Ld PLCC 0 to +70 N20.35
321 20 19
IS82C88 IS82C88 -40 to +85 N20.35
18 S2
4
DT/ R
CD82C88 CD82C88 20 Ld 0 to +70 F20.3
17 MCE/PDEN CERDIP
5
ALE
ID82C88 ID82C88 -40 to +85 F20.3
16 DEN
AEN 6
MD82C88/B MD82C88/B -55 to +125 F20.3
7 15 CEN
MRDC 8406901RA 8406901RA SMD# F20.3
14
AMWC 8 INTA MR82C88/B MR82C88/B 20 Pad CLCC -55 to +125 J20.A
13
910 11 12 84069012A 84069012A SMD# J20.A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
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S1
MWTC
GND CLK
IOWC IOB
V
AIOWC CC
S0
IORC82C8882C88
Functional Diagram
MRDC
S0
MWTC
STATUS TM
MULTIBUS
AMWC
S1 COMMAND
DECODER
COMMAND
SIGNAL IORC
S2
SIGNALS
GENERATOR
IOWC
AIOWC
INTA
DT/R
CLK
ADDRESS LATCH,
CONTROL
DEN
AEN CONTROL
DATA TRANSCEIVER,
CONTROL
SIGNAL
LOGIC
INPUT AND INTERRUPT
CEN MCE/PDEN
GENERATOR
CONTROL SIGNALS
ALE
IOB
V GND
CC
Pin Description
PIN
SYMBOL NUMBER TYPE DESCRIPTION
V 20 V : The +5V power supply pin. A 0.1F capacitor between pins 10 and 20 is recommended for decoupling.
CC CC
GND 10 GROUND.
S0, S1, S2 19, 3, 18 I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The
82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins
are not in use (passive), command outputs are held HIGH (See Table1).
CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is
active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent
D type latches, such as the 82C82 and 82C83H.
DEN 16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This
signal is active HIGH.
DT/R 4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH
on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory).
AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns
maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output
drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH).
CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control
outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode.
When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections).
AIOWC 12 O ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to
give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal.
AIOWC is active LOW.
IOWC 11 O I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal
is active LOW.
IORC 13 O I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal
is active LOW.
FN2979.2
2
August 25, 2005