ICS97ULP8 77B Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: Pin Configuration DDR2 Memory Modules / Zero Delay Board Fan Out 123456 Provides complete DDR DIMM logic solution with A ICSSSTU32864/SSTUF32864/SSTUF32866 B C Product Description/Features: D Low skew, low jitter PLL clock driver E 1 to 10 differential clock distribution (SSTL 18) F G Feedback pins for input to output synchronization H Spread Spectrum tolerant inputs J Auto PD when input signal is at a certain logic state K Switching Characteristics: 52-Ball BGA Period jitter: 40ps Top View Half-period jitter: 60ps 1234 5 6 CYCLE - CYCLE jitter 40ps A CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 OUTPUT - OUTPUT skew: 40ps B CLKC1 GND GND GND GND CLKC6 C CLKC2 GND NB NB GND CLKC7 D CLKT2 VDDQ VDDQ VDDQ OS CLKT7 E CLK INT VDDQ NB NB VDDQ FB INT F CLK INC VDDQ NB NB OE FB INC G AGND VDDQ VDDQ VDDQ VDDQ FB OUTC H AVDD GND NB NB GND FB OUTT J CLKT3 GND GND GND GND CLKT8 K CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8 Block Diagram CLKT0 CLKC0 LD* or OE OE Powerdown CLKT1 LD*, OS or OE OS Control and 40 31 CLKC1 Test Logic AV DD CLKT2 1 30 VDDQ CLKC7 CLKC2 PLL bypass LD* CLKC2 CLKT7 CLKT3 CLKT2 VDDQ CLKC3 CLK INT FB INT CLKT4 CLK INC FB INC CLKC4 ICS97ULP877B VDDQ FB OUTC CLKT5 AGND CLKC5 FB OUTT CLK INT AVDD VDDQ CLKT6 CLK INC VDDQ OE CLKC6 10K-100k GND 10 21 OS CLKT7 PLL CLKC7 GND 11 20 CLKT8 FB INT CLKC8 FB INC CLKT9 * The Logic Detect (LD) powers down the device when a CLKC9 logic low is applied to both CLK INT and CLK INC. 40-Pin MLF FB OUTT FB OUTC 0981B03/15/05 CLKT3 CLKC1 CLKC3 CLKT1 CLKC4 CLKT0 CLKT4 CLKC0 VDDQ VDDQ CLKT9 CLKC5 CLKC9 CLKT5 CLKC8 CLKT6 CLKT8 CLKC6 VDDQ VDDQICS97ULP877B Pin Descriptions Terminal Electrical Description Name Characteristics AdGND Analog Groun Ground AV Analog power 1.8 V nominal DD CrLK INT Clock input with a (10K-100K Ohm) pulldown resisto Differential input CLK INC Complentary clock input with a (10K-100K Ohm) pulldown resistor Differential input FtB INT Feedback clock inpu Differential input FtB INC Complementary feedback clock inpu Differential input FtB OUTT Feedback clock outpu Differential output FtB OUTC Complementary feedback clock outpu Differential output O)E Output Enable (Asynchronous LVCMOS input OVS Output Select (tied to GND or)tLVCMOS inpu DDQ GdND Groun Ground V Logic and output power 1.8V nominal DDQ CsLKT 0:9 Clock output Differential outputs CsLKC 0:9 Complementary clock output Differential outputs NlB No bal The PLL clock buffer, ICS97ULP877B, is designed for a V of 1.8 V, a AV of 1.8 V and differential data input and DDQ DD output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS97ULP877B is a zero delay buffer that distributes a differential clock input pair (CLK INT, CLK INC) to ten differential pair of clock outputs (CLKT 0:9 , CLKC 0:9 ) and one differential pair feedback clock outputs (FB OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK INT, CLK INC), the feedback clocks (FB INT, FB INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB OUTT/FB OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or V . When OS is high, OE will function as described above. When DDQ OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB OUTT/FB OUTC). When AV DD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK INT, CLK INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB INT, FB INC) and the input clock pair (CLK INT, CLK INC) within the specified stabilization time t . STAB The PLL in ICS97ULP877B clock driver uses the input clocks (CLK INT, CLK INC) and the feedback clocks (FB INT, FB INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT 0:9 , CLKC 0:9 ). ICS97ULP877B is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97ULP877B is characterized for operation from 0C to 70C. 0981B03/15/05 2