Si53106 SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER Features Six 0.7 V low-power, push-pull, Low phase jitter (Intel QPI, PCIe HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock outputs compliant Individual OE HW pins for each Gen 3 SRNS Compliant output clock PLL or bypass mode 100 MHz /133 MHz PLL Spread spectrum tolerable operation, supports PCIe and 1.05 to 3.3 V I/O supply voltage QPI 50 ps output-to-output skew PLL bandwidth SW SMBUS Industrial Temperature: programming overrides the latch 40 to 85 C Ordering Information: value from HW pin 40-pin QFN See page 29. SMBus address configurable to For higher output devices or allow multiple buffers in a single variations of this device, contact Patents pending control network 3.3 V supply Skyworks Solutions voltage operation Applications Server Datacenter Storage Enterprise Switches and Routers Description The Si53106 is a low-power, 6-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel Quick- Path Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Skyworks Solutions PCIe Clock Jit- ter Tool. Download it for free at Si53106 Functional Block Diagram OE 5:0 6 SSC Compatible DIF 5:0 CLK IN PLL CLK IN 100M 133 HBW BYPASS LBW SA 0 Control SA 1 Logic PWRGD / PWRDN SDA SCL 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 2, 2021