Si5345
Si5344
Si5342
Si5345/44/42
10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER
ATTENUATOR/CLOCK MULTIPLIER
Features
Generates any combination of output Optional zero delay mode
frequencies from any input frequency Fastlock feature for low nominal
Input frequency range: bandwidths
Differential: 8 kHz to 750 MHz Glitchless on the fly output frequency
LVCMOS: 8 kHz to 250 MHz changes
Output frequency range: DCO mode: as low as 0.001 ppb steps.
Differential: up to 712.5 MHz Core voltage
LVCMOS: up to 250 MHz V : 1.8 V 5%
DD
Ultra-low jitter:
V : 3.3 V 5%
DDA
<100 fs typ (12 kHz20 MHz)
Independent output clock supply pins:
Programmable jitter attenuation
3.3 V, 2.5 V, or 1.8 V
bandwidth from 0.1 Hz to 4 kHz
Output-output skew: 20 ps typ
Meets G.8262 EEC Opt 1, 2 (SyncE)
2
Serial interface: I C or SPI
Ordering Information:
Highly configurable outputs compatible
In-circuit programmable with
with LVDS, LVPECL, LVCMOS, CML,
See section 8
non-volatile OTP memory
and HCSL with programmable signal
TM
ClockBuilder Pro software simplifies
amplitude
device configuration Functional Block Diagram
Status monitoring (LOS, OOF, LOL)
Si5345: 4 input, 10 output, 64 QFN
Hitless input clock switching: automatic
Si5344: 4 input, 4 output, 44 QFN
or manual
Si5342: 4 input, 2 output, 44 QFN
XTAL
Locks to gapped clock inputs
Temperature range: 40 to +85 C
Automatic free-run and holdover
Pb-free, RoHS-6 compliant
XB
Si5345/44/42
modes XA
IN_SEL
Device Selector Guide
OSC
IN0 FRAC
Grade Max Output Frequency Frequency Synthesis Modes
FRAC
IN1
Si534fA 712.5 MHz Integer+Fractional DSPLL
IN2 FRAC
Si534fB 350 MHz Integer+Fractional
IN3/
FRAC
FB_IN
Si534fC 712.5 MHz Integer
Optional
External
Si534fD 350 MHz Integer
Feedback
Applications
Multi
INT
OUT0
Synth
OTN Muxponders and Transponders Carrier Ethernet switches
Multi
10/40/100G networking line cards SONET/SDH Line Cards
INT
OUT1
Synth
GbE/10GbE/100GbE Synchronous Broadcast video
Multi
INT
OUT2
Ethernet (ITU-T G.8262) Test and measurement
Synth
ITU-T G.8262 (SyncE) Compliant
Multi
INT
OUT3
Synth
Description
Multi
INT
OUT4
Synth
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
INT
OUT5
MultiSynth technologies to enable any-frequency clock generation and jitter
attenuation for applications requiring the highest level of jitter performance. These
NVM INT
OUT6
devices are programmable via a serial interface with in-circuit programmable non-
2
I C/SPI
INT
volatile memory (NVM) so they always power up with a known frequency configuration. OUT7
They support free-run, synchronous, and holdover modes of operation, and offer both
Control/
INT
OUT8
automatic and manual input clock switching. The loop filter is fully integrated on-chip,
Status
eliminating the risk of noise coupling associated with discrete solutions. Further, the
INT
OUT9
jitter attenuation bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Programming the Si5345/44/42 is easy with Silicon
Labs ClockBuilder Pro software. Factory preprogrammed devices are also available.
Rev. 1.0 7/15 Copyright 2015 by Silicon Laboratories Si5345/44/42Si5345/44/42
TABLE OF CONTENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.13. Enabling Features and/or Configuration Settings Unavailable in
ClockBuilder Pro for Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . .43
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . .57
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2 Rev. 1.0