W25Q02JV-DTR 3.0V 2G-BIT (QUAD DIE) SERIAL FLASH MEMORY WITH DUAL/QUAD SPI, QPI & DTR Publication Release Date: April 19, 2021 - 1 - -Revision B W25Q02JV-DTR Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 6 2. FEATURES ....................................................................................................................................... 7 3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 8 3.1 Ball Configuration TFBGA 8x6-mm (5x5 Ball Array) ............................................................ 8 3.2 Ball Description TFBGA 8x6-mm ......................................................................................... 8 4. PIN DESCRIPTIONS ........................................................................................................................ 9 4.1 Chip Select (/CS) .................................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9 4.3 Write Protect (/WP) .............................................................................................................. 9 4.4 HOLD (/HOLD) ..................................................................................................................... 9 4.5 Serial Clock (CLK) ................................................................................................................ 9 4.6 Reset (/RESET) .................................................................................................................... 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11 6.1 SPI / QPI Operations .......................................................................................................... 11 6.1.1 Standard SPI Instructions ..................................................................................................... 11 6.1.2 Dual SPI Instructions ............................................................................................................ 11 6.1.3 Quad SPI Instructions ........................................................................................................... 12 6.1.4 QPI Instructions .................................................................................................................... 12 6.1.5 SPI / QPI DTR Read Instructions ......................................................................................... 12 6.1.6 3-Byte / 4-Byte Address Modes ............................................................................................ 12 6.1.7 Hold Function ....................................................................................................................... 13 6.1.8 Software Reset & Hardware /RESET pin .............................................................................. 13 6.2 Write Protection .................................................................................................................. 14 7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 16 7.1 Status Registers ................................................................................................................. 16 7.1.1 Program/Erase/Write In Progress (BUSY) Status Only ..................................................... 16 7.1.2 Write Enable Latch (WEL) Status Only ............................................................................. 16 7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) Volatile/Non-Volatile Writable .......................... 17 7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable .......................................... 17 7.1.5 Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................... 17 7.1.6 Status Register Protect (SRP, SRL) Volatile/Non-Volatile Writable .................................. 17 7.1.7 Erase/Program Suspend Status (SUS) Status Only .......................................................... 18 7.1.8 Security Register Lock Bits (LB3, LB2, LB1) Non-Volatile OTP Writable .......................... 18 7.1.9 Quad Enable (QE) Volatile/Non-Volatile Writable ............................................................. 18 7.1.10 Current Address Mode (ADS) Status Only ...................................................................... 19 7.1.11 Power-Up Address Mode (ADP) Non-Volatile Writable ................................................... 19 7.1.12 Write Protect Selection (WPS) Volatile/Non-Volatile Writable ........................................ 19 7.1.13 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable ............................. 19 7.1.14 /HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable .................. 20 Publication Release Date: April 19, 2021 - 2 - -Revision B