SiC MOSFET Isolated Gate Driver SiC MOSFET Isolated Gate Driver This article describes an implementation of an isolated gate driver suitable for testing and evaluating SiC MOSFETs in a variety of applications. This design replaces previous versions of this application note and include new enhancements. The enhancements are as follows: The circuit board has been extended so that now 2 watt as well as 1 watt DC-DC converters can be used. This enables driving larger MOSFETs or driving of smaller MOSFETs at higher frequency. The creep/strike clearance has been significantly increased. A separate regulator has been added for the opto-isolator. This allows simpler bypassing of the DC-DC converters when non-isolated operation is desired. The output resistor network has been modified with an additional diode to allow separate optimization of turn-on and turn-off transitions. The top and bottom view of the enhanced gate driver is shown in Figures 1 and 2. The enhanced creep distance is accomplished with the groove in the printed circuit card. Some of the components are not populated because of the added flexibility in setting up the output network. Figure 1: Isolated Gate Driver Top View Figure 2: Isolated Gate Driver Bottom View The new schematic for the enhanced gate driver is shown in Figure 3. The circuit consists of two isolated DC-DC converters (X2 and X3), an opto-isolator (U1) and the gate driver inte- grated circuit (U2). This integrated circuit, the Clare/IXYS IXDN609SI can provide 35V output swing and up to 9A of current with a typical output resistance of 0.8 . The opto-isolator, the Avago ACPL-4800-300E, has high common mode transient immunity (30kV/sec) and can operate from 4.5 to 20V. A provision for an input filtering capacitor (C4) has been included if needed. Power is provided by isolated DC-DC converters one for the positive bias and the other for negative bias. X2 and X3 are both from the Recom RP series of 1 watt unregulated isolated DC-DC converters or the Recom 1 RxxP2xx series of 2 watt DC-DC converters. Ei- ther type can be accommodated depending on the application. Subject to change without notice. 1 www.cree.com CPWR-AN10, REV -C SiC MOSFET Isolated Gate Driver These converters are inexpensive with an isolation voltage rating of 5.2kV and also have very low isolation capacitance. In this particular configuration, X2 is a 12V in 5V out converter and X3 is a 12V in, +/-12V out converter. As shown in the schematic, the outputs of the converters are series connected and the common connection is referenced to the source terminal. Therefore, VCC determines the gate pulse positive voltage and VEE determines the negative gate pulse voltage. The VEE node is used as the ground reference for opto-isolator and the gate driver. The opto-isolators maximum operating voltage is 20V which can be greater than the voltage appearing at VCC. An emitter follower clam consisting of Q1 and D1 has been added to limit the voltage to the opto-isolator to 17.3V nominal. A base resistor (R16) was included if additional dampening is desired for the emitter follower. In practice, a zero ohm resistor works fine. Resistors R2, R4, R5, R9-R15 and diode D2 can be populated to provide optimum turn-on and turn-off performance. In this case, only R2, R4 and R5 are populated with 20 ohm 1/3 watt resistors. To minimize stray inductance, capacitors C8- C10 are located very close to the source output pin and the gate driver to provide very tight coupling between the source output terminal and the VEE node. Figure 3: Isolated Gate Driver Schematic R15 0.100 ISOLATION THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE BOUNDRY SLIT 20 R14 BOARD IF REQ. +VCC 20 R13 X3 C1 20 R1 1 7 1U R12 VCC HIGH +VIN +VOUT 10K 0603 0805 6 COM 20 Q1 D2 R16 0 2 5 C2 DXT2222A DIODE VCC HIGH RTN -VIN -VOUT 1U 0805 0603 R11 20 1210 RP-1212D D1 R10 20 1210 MMSZ5248B-7-F X2 C3 1 7 1U VCC LOW +VIN +VOUT 0603 R9 20 1210 SOURCE -VEE -VEE 2 5 VCC LOW RTN -VIN -VOUT R2 20 1210 RP-1205S -VEE U1 R3 620 R4 20 1210 GATE 1 8 +VCC +VCC INPUTHIGH NC VCC C5 U2 0805 2 7 100N 1 8 ANODE NC VCC VCC C4 0805 R5 20 1210 JP1 TBD 3 6 2 7 CATH VO IN OUT 7 R6 620 0805 8 4 5 R7 C6 3 6 C7 INPUTLOW NC GND NC OUT 9 47K 100N 4.7U R8 0805 ACPL-4800-300E -VEE 0603 0805 4 5 1206 47K HEADER 3 GND GND 0603 J2 -VEE JP2 IXDN609SI VCC HIGH -VEE -VEE C8 10 11 1 VCC HIGH RTN 10N 1210 12 2 -VEE INPUTHIGH 3 C9 HEADER 3 4 SOURCE 5 INPUTLOW 100N 6 -VEE VCC LOW C10 VCC LOW RTN 10U 1210 HEADER 6 -VEE SOURCE Operation of the gate driver is as follows. A +10 to +12V pulse is applied to the opto causes the gate terminal to go high. The intent of this circuit is to afford the maximum flexibility. Therefore, unregulated DC-DC converters were used so that the output gate pulse positive and negative voltage levels can be adjusted at ground level. The gate voltage positive level is adjusted by varying the voltage between the VCC HIGH and VCC HIGH RTN and the negative pulse level is adjusted by varying the voltage between the VCC LOW and VCC LOW RTN pins. The procedure is to observe the output of the gate driver board with an oscilloscope and adjust VCC HIGH and VCC LOW input voltages until the gate pulse is set to the desired values. Care must be taken during adjustment to insure that the voltage between the VCC and VEE nodes does not exceed the maximum ratings of U2, which is 35V. This document is provided for informational purposes only and is not a warranty or a specification. CPWR-AN10, REV -C For product specifications, please see the data sheets available at www.cree.com/power. For warranty SiC MOSFET Isolated Gate Driver information, please contact Cree Sales at PowerSales cree.com. 2