A3R2GE43JBF-8E Zentel

Doc. No. DSA3R2GE43JBFF.01 A3R2GE43JBF 2Gb DDR2 SDRAM 2Gb DDR2 SDRAM Specification Specifications Features Density: 2G bits Double data-rate architecture: two data transfers per Organization clock cycle o 8 banks x 16M words x 16 bits The high-speed data transfer is realized by the 4 bits Package prefetch pipelined architecture o 84-ball FBGA (x16) Bi-directional differential data strobe (DQS and /DQS) is o Lead-free(RoHS compliant) transmitted/received with data for capturing data at the Power supply receiver o V ,V =1.7 to 1.9V DD DDQ DQS is edge-aligned with data for READs center- aligned Data Rate: 1066Mbps/800Mbps with data for WRITEs 2KB page size (x16) Differential clock inputs (CK and /CK) o Row address: AX0 to AX13 DLL aligns DQ and DQS transitions with CK transitions o Column address: AY0 to AY9 Commands entered on each positive CK edge data and Eight internal banks for concurrent operation data mask referenced to both edges of DQS Interface: SSTL 18 Data mask (DM) for write data o Burst lengths (BL): 4 , 8 Posted CAS by programmable additive latency for better Burst type (BT): command and data bus efficiency o Sequential On-Die-Termination for better signal quality o Interleave Programmable RDQS, /RDQS output for making x8 CAS latency (CL): 3, 4, 5, 6, 7 organization compatible with x4 organization Precharge: Auto precharge option for each burst access /DQS, (/RDQS) can be disabled for single-ended Data Driver strength: Normal/Weak Strobe operation Low self-refresh current (IDD6) parts are available Off-Chip Driver (OCD) impedance adjustment is not Refresh: auto-refresh, self-refresh supported Refresh cycles: 8192 cycles/64ms o Average auto-refresh period 7.8us at TC +85 3.9us at TC > +85 Operating case temperature range o TC = 0C to +85C (Commercial grade) Rev. 01 Dec. 22, 2020 1 of 25 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3R2GE43JBFF.01 A3R2GE43JBF 2Gb DDR2 SDRAM Table of Contents 2Gb DDR2 SDRAM Specification ...................................................................................................................... 1 1. Ordering Information ............................................................................................................................ 3 2. Package Ball Assignment ....................................................................................................................... 4 3. Package outline drawing........................................................................................................................ 5 4. Electrical Specifications: ........................................................................................................................ 6 5. Block Diagram ..................................................................................................................................... 15 6. Pin function ......................................................................................................................................... 16 7. Command Operation ........................................................................................................................... 18 8. Functional Description ......................................................................................................................... 19 Rev. 01 Dec. 22, 2020 2 of 25 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.