SKU85 Zipcores

CONV YC Chroma Resampler Rev. 1.0 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Conversion of pixels between 4:4:4 and 4:2:2 YCbCr formats Supports 10-bit Luma and Chroma samples Fully pipelined architecture with simple flow control Features VSYNC and HSYNC sideband flags to keep track of video frame and line boundaries Output 1 x pixel per clock Small implementation size Support for 400 MHz+ operation on basic FPGA devices Applications Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats Pin-out Description Pin name I/O Description Active state clk in Synchronous clock rising edge reset in Asynchronous reset low pixin y 9:0 in Luma Component data pixin cb 9:0 in Chroma (Blue) component data pixin cr 9:0 in Chroma (Red) component data Figure 1: Chroma resampler architecture pixin c 9:0 in Multiplexed Chroma value data (4:2:2 formats) pixin vsync in Vertical sync flag in high General Description pixin hsync in Horizontal sync flag in high pixin val in Input pixel valid high The CONV YC IP Core (Figure 1) is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour pixin rdy out Input pixel ready high space. In total, the IP Core package contains two distinct modules one pixout y 9:0 out Luma Component data module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. pixout cb 9:0 out Chroma (Blue) component data Pixels flow into the design in accordance with the valid ready pipeline pixout cr 9:0 out Chroma (Red) component data 1 protocol . Input pixels and syncs are sampled on the rising edge of clk pixout c 9:0 out Multiplexed Chroma value data when pixin val and pixin rdy are both high. At the output interface, pixels (4:2:2 formats) and syncs are sampled on a the rising edge of clk when pixout val and pixout rdy are high. The input and output sync signals are coincident pixout vsync out Vertical sync flag out high with the first pixel of a frame and the first pixel of a line. These are useful pixout hsync out Horizontal sync flag out high to identify the video frame and line boundaries. The pixin hsync signal is also used to ensure that pixels are aligned correctly at the converter pixout val out Output pixel valid high inputs. pixout rdy in Output pixel ready high Note that if no flow control is required in the design and the output interface can always accept pixels, then the pixout rdy signal may be tied high. Likewise, the pixin rdy flag may be ignored in this case. 1 See Zipcores application note: app note zc001.pdf for more examples of how to use the valid-ready pipeline protocol Copyright 2013 www.zipcores.com Download this VHDL Core Page 1 of 1X-ON Electronics Largest Supplier of Electrical and Electronic Components Click to view similar products for Development Software category: Click to view products by Zipcores manufacturer: Other Similar products are found below : SRP004001-01 SW163052 SYSWINEV21 WS01NCTF1E W128E13 SW89CN0-ZCC IP-UART-16550 MPROG-PRO535E AFLCF-08- LX-CE060-R21 WS02-CFSC1-EV3-UP SYSMAC-STUDIO-EIPCPLR 1120270005 SW006021-2H ATATMELSTUDIO 2400573 2702579 2988609 SW006022-DGL 2400303 88970111 DG-ACC-NET-CD 55195101-101 55195101-102 SW1A-W1C MDK-ARM SW006021-2NH B10443 SW006021-1H SW006021-2 SW006022-2 SW006023-2 SW007023 MIKROE-730 MIKROE-2401 MIKROE-499 MIKROE-722 MIKROE-724 MIKROE-726 MIKROE-728 MIKROE-732 MIKROE-734 MIKROE-736 MIKROE-738 MIKROE-744 MIKROE-928 MIKROE-936 1120270002 1120270003 1120275015 NT-ZJCAT1-EV4