FUJITSU SEMICONDUCTOR DATA SHEET DS501-00015-4v0-E Memory FRAM 64 K (8 K 8) Bit SPI MB85RS64V DESCRIPTION MB85RS64V is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS64V adopts the Serial Peripheral Interface (SPI). The MB85RS64V is able to retain data without using a back-up battery, as is needed for SRAM. 12 The memory cells used in the MB85RS64V can be used for 10 read/write operations, which is a significant 2 improvement over the number of read and write operations supported by Flash memory and E PROM. 2 MB85RS64V does not take long time to write data like Flash memories or E PROM, and MB85RS64V takes no wait time. FEATURES Bit configuration : 8,192 words 8 bits Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Operating frequency : 20 MHz (Max) 12 High endurance : 10 times / byte Data retention : 10 years ( + 85 C), 95 years ( + 55 C), over 200 years ( + 35 C) Operating power supply voltage : 3.0 V to 5.5 V Low power consumption : Operating power supply current 1.5 mA (Typ 20 MHz) Standby current 10 A (Typ) Operation ambient temperature range : 40 C to + 85 C Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.9MB85RS64V PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD 2 7 SO HOLD 3 6 WP SCK 4 5 GND SI (FPT-8P-M02) PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description Chip Select pin This is an input pin to make chip select. When CS is the H level, device is in deselect 1CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When CS is the L level, device is in select (active) status. CS has to be the L level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. Write Protect pin This is a pin to control writing to a status register. The writing of status register (see 3WP STATUS REGISTER) is protected in related with WP and WPEN. See WRITING PROTECT for detail. Hold pin This pin is used to interrupt serial input/output without making chip deselect. When 7HOLD HOLD is the L level, hold operation is activated, SO becomes High-Z, and SCK and SI become dont care. While the hold operation, CS shall be retained the L level. Serial Clock pin 6SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin 2 DS501-00015-4v0-E