TSL202R 128 1 LINEAR SENSOR ARRAY TAOS032E AUGUST 2011 128 1 Sensor-Element Organization (TOP VIEW) 200 Dots-Per-Inch (DPI) Sensor Pitch V 1 14 NC DD High Linearity and Uniformity SI1 2 13 SO1 Wide Dynamic Range . 2000:1 (66 dB) Output Referenced to Ground CLK 3 12 GND Low Image Lag . 0.5% Typ AO1 4 11 NC Operation to 5 MHz GND 5 10 SI2 Single 5-V Supply 9 NC SO2 6 Replacement for TSL202 8 AO2 NC 7 NC No internal connection Description The TSL202R linear sensor array consists of two sections of 64 photodiodes and associated charge amplifier circuitry arranged to form a contiguous 128 1 array. The pixels measure 120 m (H) by 70 m (W) with 125-m center-to-center spacing and 55-m spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. The TSL202R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear and rotary encoding. Functional Block Diagram (each section pin numbers apply to section 1) 1 Pixel 1 Pixel Pixel Pixel 1 Integrator V DD 2 3 64 Reset S1 2 Output Amplifier Analog 2 1 3 Bus 4 + AO S2 R L Sample/ (External Output 5 330 GND Load) Gain Switch Control Logic Trim Q1 Q2 Q3 Q64 3 CLK 64-Bit Shift Register 2 SI The LUMENOLOGY Company Copyright 2011, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road Suite 300 Plano, TX 75074 (972) 673-0759 www.taosinc.com 1TSL202R 128 1 LINEAR SENSOR ARRAY TAOS032E AUGUST 2011 Terminal Functions TERMINAL NAME NO. DESCRIPTION AO1 4 Analog output of section 1 AO2 8 Analog output of section 2 CLK 3 Clock. Clk controls charge transfer, pixel output, and reset. GND 5,12 Ground (substrate). All voltages are referenced to GND. NC 7, 9, 11, 14 No internal connection SI1 2 Serial input (section 1). SI1 defines the start of the data-out sequence. SI2 10 Serial input (section 2). SI2 defines the start of the data-out sequence. SO1 13 Serial output (section 1). SO1 provides a signal to drive the SI2 input. Serial output (section 2). SO2 provides a signal to drive the SI input of another device for SO2 6 cascading or as an end-of-data indication. V 1 Supply voltage. Supply voltage for both analog and digital circuitry. DD Detailed Description The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2) . As the SI pulse is clocked through the 128-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes th low, the pixel integrator is reset. On the 129 clock rising edge, the SI pulse is clocked out of the shift register th and the output assumes a high-impedance state. Note that this 129 clock pulse is required to terminate the th output of the 128 pixel and return the internal logic to a known state. A subsequent SI pulse can be presented th as early as the 130 clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output (AO) is given by: V = V + (R ) (E ) (t ) out drk e e int where: V is the analog output voltage for white condition out V is the analog output voltage for dark condition drk 2 R is the device responsivity for a given wavelength of light given in V/(J/cm ) e 2 E is the incident irradiance in W/cm e t is integration time in seconds int AO is driven by a source follower that requires an external pulldown resistor (330- typical). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state. A 0.1 F bypass capacitor should be connected between V and ground as close as possible to the device. DD For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. Copyright 2011, TAOS Inc. The LUMENOLOGY Company 2 www.taosinc.com