Single-Supply a 16-Bit Stereo ADC AD1877 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 5 V Power Supply Single-Ended Dual-Channel Analog Inputs CLOCK 92 dB (Typ) Dynamic Range LRCK 1 CLKIN 28 DIVIDER SERIAL OUTPUT 90 dB (Typ) S/(THD+N) INTERFACE WCLK TAG 2 27 0.006 dB Decimator Passband Ripple Fourth-Order, 64-Times Oversampling Modulator BCLK 3 SOUT 26 Three-Stage, Linear-Phase Decimator THREE-STAGE FIR THREE-STAGE FIR 4 DV 2 DV 1 25 DD DD DECIMATION 256 F or 384 F Input Clock DECIMATION S S FILTER FILTER DGND1 Less than 100 W (Typ) Power-Down Mode 5 24 DGND2 Input Overrange Indication RDEDGE 23 6 RESET On-Chip Voltage Reference D D D D A A A A 7 S/M 22 MSBDLY Flexible Serial Output Interface C C C C 28-Lead SOIC Package 384/256 8 21 RLJUST APPLICATIONS AV 9 20 AGND DD Consumer Digital Audio Receivers V L 10 V R 19 IN IN Digital Audio Recorders, Including Portables CD-R, DCC, MD and DAT CAPL1 11 18 CAPR1 Multimedia and Consumer Electronic Equipment CAPL2 12 17 CAPR2 SINGLE TO SINGLE TO Sampling Music Synthesizers DIFFERENTIAL INPUT DIFFERENTIAL INPUT CONVERTER CONVERTER AGNDR Digital Karaoke Systems AGNDL 13 16 VOLTAGE V R V L 14 15 REF REF REFERENCE AD1877 PRODUCT OVERVIEW The AD1877 is a stereo, 16-bit oversampling ADC based on Sigma Delta ( ) technology intended primarily for digital one-bit comparators quantization noise out of the audio pass- audio bandwidth applications requiring a single 5 V power supply. band. The high order of the modulator randomizes the modulator Each single-ended channel consists of a fourth-order one-bit output, reducing idle tones in the AD1877 to very low levels. noise shaping modulator and a digital decimation filter. An on- Because its modulator is single-bit, AD1877 is inherently chip voltage reference, stable over temperature and time, defines monotonic and has no mechanism for producing differential the full-scale range for both channels. Digital output data from linearity errors. both channels are time-multiplexed to a single, flexible serial interface. The AD1877 accepts a 256 F or a 384 F input S S The input section of the AD1877 uses autocalibration to correct clock (F is the sampling frequency) and operates in both serial S any dc offset voltage present in the circuit, provided that the inputs port master and slave modes. In slave mode, all clocks must are ac coupled. The single-ended dc input voltage can swing be externally derived from a common source. between 0.7 V and 3.8 V typically. The AD1877 antialias input circuit requires four external 470 pF NPO ceramic chip filter Input signals are sampled at 64 F onto internally buffered S capacitors, two for each channel. No active electronics are switched-capacitors, eliminating external sample-and-hold ampli- needed. Decoupling capacitors for the supply and reference pins fiers and minimizing the requirements for antialias filtering at the are also required. input. With simplified antialiasing, linear phase can be preserved across the passband. The on-chip single-ended to differential signal The dual digital decimation filters are triple-stage, finite impulse converters save the board designer from having to provide them response filters for effectively removing the modulators high externally. The AD1877s internal differential architecture provides frequency quantization noise and reducing the 64 F single-bit S increased dynamic range and excellent power supply rejection output data rate to an F word rate. They provide linear phase S characteristics. The AD1877s proprietary fourth-order differen- and a narrow transition band that properly digitizes 20 kHz signals tial switched-capacitor modulator architecture shapes the at a 44.1 kHz sampling frequency. Passband ripple is less than 0.006 dB, and stopband attenuation exceeds 90 dB. (Continued on Page 6) REV. A IInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD1877SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages 5.0 V Ambient Temperature 25 C Input Clock (F ) 256 F 12.288 MHz CLKIN S Input Signal 991.768 Hz 0.5 dB Full Scale Measurement Bandwidth 23.2 Hz to 19.998 kHz Load Capacitance on Digital Outputs 50 pF Input Voltage HI (V ) 2.4 V IH Input Voltage LO (V ) 0.8 V IL 2 Master Mode, Data I S-Justified (Refer to Figure 14). Device Under Test (DUT) bypassed and decoupled as shown in Figure 3. DUT is antialiased and ac coupled as shown in Figure 2. DUT is calibrated. Values in bold typeface are tested, all others are guaranteed but not tested. ANALOG PERFORMANCE Min Typ Max Unit Resolution 16 Bits Dynamic Range (20 Hz to 20 kHz, 60 dB Input) Without A-Weight Filter 87 92 dB With A-Weight Filter 90 94 dB Signal to (THD + Noise) 86.5 90 dB Signal to THD 92 94 dB Analog Inputs Single-Ended Input Range ( Full Scale)* V 1.55 V V + 1.55 V REF REF REF Input Impedance at Each Input Pin 32 k V 2.05 2.25 2.55 V REF DC Accuracy Gain Error 0.5 2.5 % Interchannel Gain Mismatch 0.01 dB Gain Drift 115 ppm/C Midscale Offset Error (After Calibration) 3 20 LSBs Midscale Drift 15 ppm/C Crosstalk (EIAJ Method) 90 99 dB *V p-p = V 1.333. IN REF 2 REV. A