Product Information

AD600JN

AD600JN electronic component of Analog Devices

Datasheet
Differential Amplifiers DUAL VARIABLE GAIN AMP IC

Manufacturer: Analog Devices
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1: USD 161.1666 ea
Line Total: USD 161.1666

4 - Global Stock
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Fri. 05 Apr to Thu. 11 Apr
MOQ: 1  Multiples: 1
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4 - Global Stock


Ships to you between Fri. 05 Apr to Thu. 11 Apr

MOQ : 1
Multiples : 1

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AD600JN
Analog Devices

1 : USD 159.8875
5 : USD 56.2875

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Series
Number of Channels
GBP - Gain Bandwidth Product
CMRR - Common Mode Rejection Ratio
Supply Current per Channel
Ib - Input Bias Current
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Maximum Dual Supply Voltage
Maximum Input Resistance
Operating Supply Voltage
Single Supply Voltage
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Dual, Low Noise, Wideband Variable Gain Amplifiers AD600/AD602 FEATURES FUNCTIONAL BLOCK DIAGRAM GAT1 2 channels with independent gain control Linear in dB gain response PRECISION PASSIVE SCALING GATING INPUT ATTENUATOR 2 gain ranges REFERENCE INTERFACE AD600: 0 dB to 40 dB C1HI V G A1OP AD602: 10 dB to +30 dB C1LO Accurate absolute gain: 0.3 dB A1CM GAIN CONTROL Low input noise: 1.4 nV/Hz INTERFACE RF2 2.24k (AD600) Low distortion: 60 dBc THD at 1 V output 0dB 12.04dB 22.08dB 36.12dB 694 (AD602) High bandwidth: dc to 35 MHz (3 dB) 6.02dB 18.06dB 30.1dB 42.14dB RF1 20 Stable group delay: 2 ns A1HI FIXED-GAIN Low power: 125 mW (maximum) per amplifier AMPLIFIER A1LO 500 62.5 41.07dB (AD600) R-2R LADDER NETWORK Signal gating function for each amplifier 31.07dB (AD602) Drive high speed ADCs Figure 1. Functional Block Diagram of a Single Channel of the AD600/AD602 MIL-STD-883-compliant and DESC versions available The gain-control interfaces are fully differential, providing an APPLICATIONS input resistance of ~15 M and a scale factor of 32 dB/V (that Ultrasound and sonar time-gain controls is, 31.25 mV/dB) defined by an internal voltage reference. The High performance audio and RF AGC systems response time of this interface is less than 1 s. Each channel Signal measurement also has an independent gating facility that optionally blocks signal transmission and sets the dc output level to within a few GENERAL DESCRIPTION millivolts of the output ground. The gating control input is 1 The AD600/AD602 dual-channel, low noise, variable gain TTL- and CMOS-compatible. amplifiers are optimized for use in ultrasound imaging systems The maximum gain of the AD600 is 41.07 dB, and the maximum but are applicable to any application requiring precise gain, low gain of the AD602 is 31.07 dB the 3 dB bandwidth of both noise and distortion, and wide bandwidth. Each independent models is nominally 35 MHz, essentially independent of the channel provides a gain of 0 dB to +40 dB in the AD600 and gain. The SNR for a 1 V rms output and a 1 MHz noise 10 dB to +30 dB in the AD602. The lower gain of the AD602 bandwidth is typically 76 dB for the AD600 and 86 dB for the results in an improved signal-to-noise ratio (SNR) at the output. AD602. The amplitude response is flat within 0.5 dB from However, both products have the same 1.4 nV/Hz input noise 100 kHz to 10 MHz over this frequency range, the group delay spectral density. The decibel gain is directly proportional to the varies by less than 2 ns at all gain settings. control voltage, accurately calibrated, and supply and temper- ature stable. Each amplifier channel can drive 100 load impedances with low distortion. For example, the peak specified output is 2.5 V To achieve the difficult performance objectives, a proprietary minimum into a 500 load or 1 V into a 100 load. For a circuit form, the X-AMP, was developed. Each channel of the 200 load in shunt with 5 pF, the total harmonic distortion for X-AMP comprises a variable attenuator of 0 dB to 42.14 dB a 1 V sinusoidal output at 10 MHz is typically 60 dBc. followed by a high speed fixed gain amplifier. In this way, the amplifier never has to cope with large inputs and can benefit The AD600J/AD602J are specified for operation from 0C to 70C from the use of negative feedback to precisely define the gain and are available in 16-lead PDIP (N) and 16-lead SOIC packages. and dynamics. The attenuator is realized as a 7-stage R-2R The AD600A/AD602A are specified for operation from 40C to ladder network having an input resistance of 100 , laser +85C and are available in 16-lead CERDIP (Q) and 16-lead SOIC trimmed to 2%. The attenuation between tap points is 6.02 dB packages. The AD600S/AD602S are specified for operation from the gain-control circuit provides continuous interpolation between 55C to +125C, are available in a 16-lead CERDIP (Q) package, these taps. The resulting control function is linear in dB. and are MIL-STD-883-compliant. The AD600S/AD602S are also available under DESC SMD 5962-94572. 1 Patented. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00538-001AD600/AD602 TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 Time-Gain Control (TGC) and Time-Variable Gain (TVG) ................................................................................. 15 General Description ......................................................................... 1 Increasing Output Drive ............................................................ 15 Functional Block Diagram .............................................................. 1 Driving Capacitive Loads .......................................................... 15 Revision History ............................................................................... 2 Realizing Other Gain Ranges ................................................... 16 Specif icat ions ..................................................................................... 3 Ultralow Noise VCA .................................................................. 16 Absolute Maximum Ratings ............................................................ 5 Low Noise, 6 dB Preamplifier ................................................... 16 ESD Caution .................................................................................. 5 Low Noise AGC Amplifier with 80 dB Gain Range .............. 17 Pin Configuration and Function Descriptions ............................. 6 Wide Range, RMS-Linear dB Measurement System Typical Performance Characteristics ............................................. 7 (2 MHz AGC Amplifier with RMS Detector) ........................ 19 Theory of Operation ...................................................................... 10 100 dB to 120 dB RMS Responding Constant Bandwidth Noise Performance ..................................................................... 10 AGC Systems with High Accuracy Decibel Outputs ............ 21 Gain-Control Interface .............................................................. 11 100 dB RMS/AGC System with Minimal Gain Error Signal-Gating Inputs .................................................................. 11 (Parallel Gain with Offset) ........................................................ 22 Common-Mode Rejection ........................................................ 11 120 dB RMS/AGC System with Optimal SNR (Sequential Gain) ....................................................................... 23 Achieving 80 dB Gain Range .................................................... 11 Outline Dimensions ....................................................................... 27 Sequential Mode (Maximum SNR) ......................................... 12 Ordering Guide .......................................................................... 29 Parallel Mode (Simplest Gain-Control Interface) .................. 13 Low Ripple Mode (Minimum Gain Error) ............................. 13 REVISION HISTORY 10/08Rev. E to Rev. F 5/02Rev. B to Rev. C Changes to Power Supply Parameter, Table 1 ............................... 3 Changes to Specifications ................................................................. 2 Changes to Figure 41 ...................................................................... 20 Renumber Tables and TPCs ................................................... Global Changes to Figure 45 ...................................................................... 21 8/01Rev. A to Rev. B Changes to Figure 47 ...................................................................... 22 Changes to Accuracy Section of AD600A/AD602A column ...... 2 Changes to Figure 51 ...................................................................... 24 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 29 1/06Rev. D to Rev. E Updated Format .................................................................. Universal Changes to Table 2 ............................................................................ 5 Changes to The Gain-Control Interface Section ........................ 11 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 3/04Rev. C to Rev. D Changes to Specifications ................................................................ 2 Changes to Ordering Guide ............................................................ 3 Changes to Figure 3 .......................................................................... 8 Changes to Figure 29 ...................................................................... 18 Updated Outline Dimensions ....................................................... 20 Rev. F Page 2 of 32

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8542.33.00 43 No -- Amplifiers

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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