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AD724JRZ

AD724JRZ electronic component of Analog Devices

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Video ICs SOIC LP/SS RGB-NTSC/PAL ENCODER

Manufacturer: Analog Devices
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1: USD 17.8228 ea
Line Total: USD 17.82

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AD724JRZ
Analog Devices

1 : USD 20.1839
10 : USD 18.5597
25 : USD 17.7904

     
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a RGB to NTSC/PAL Encoder AD724 FEATURES operates from a single +5 V supply. No external delay lines or Low Cost, Integrated Solution filters are required. The AD724 may be powered down when +5 V Operation not in use. Accepts FSC Clock or Crystal, or 4FSC Clock The AD724 accepts either FSC or 4FSC clock. When a clock is Composite Video and Separate Y/C (S-Video) Outputs not available, a low cost parallel-resonant crystal (3.58 MHz Luma and Chroma Outputs Are Time Aligned (NTSC) or 4.43 MHz (PAL)) and the AD724s on-chip oscilla- Minimal External Components: tor generate the necessary subcarrier clock. The AD724 also No External Filters or Delay Lines Required accepts the subcarrier clock from an external video source. Onboard DC Clamp The interface to graphics controllers is simple: an on-chip logic Accepts Either HSYNC and VSYNC or CSYNC XNOR accepts the available vertical (VSYNC) and horizon- Phase Lock to External Subcarrier tal sync (HSYNC) signals and creates the composite sync Drives 75 V Reverse-Terminated Loads (CSYNC) signal on-chip. If available, the AD724 will also Logic Selectable NTSC or PAL Encoding Modes accept a standard CSYNC signal by connecting VSYNC to Compact 16-Lead SOIC Logic HI and applying CSYNC to the HSYNC pin. The APPLICATIONS AD724 contains decoding logic to identify valid horizontal sync RGB to NTSC or PAL Encoding pulses for correct burst insertion. Delays in the U and V chroma filters are matched by an on-chip PRODUCT DESCRIPTION sampled-data delay line in the Y signal path. To prevent alias- The AD724 is a low cost RGB to NTSC/PAL Encoder that ing, a prefilter at 5 MHz is included ahead of the delay line and converts red, green and blue color component signals into their a post-filter at 5 MHz is added after the delay line to suppress corresponding luminance (baseband amplitude) and chromi- harmonics in the output. These low-pass filters are optimized nance (subcarrier amplitude and phase) signals in accordance for minimum pulse overshoot. The overall luma delay, relative with either NTSC or PAL standards. These two outputs are also to chroma, has been designed to be time aligned for direct input to combined to provide composite video output. All three outputs can a televisions baseband. The AD724 comes in a space-saving simultaneously drive 75 W , reverse-terminated cables. All logi- SOIC and is specified for the 0 C to +70 C commercial tem- cal inputs are TTL, 3 V and 5 V CMOS compatible. The chip perature range. FUNCTIONAL BLOCK DIAGRAM PHASE DETECTOR FSC LOOP 4FSC SUB- CHARGE XOSC PUMP FILTER VCO CARRIER 4FSC 4FSC FSC CSYNC SYNC NTSC/PAL SEPARATOR BURST HSYNC NTSC/PAL XNOR VSYNC CSYNC 180 SC 90/270 FSC 90 QUADRATURE 4FSC (PAL ONLY) +4 FSC 0 DECODER CLOCK AT 8FSC CSYNC 3-POLE SAMPLED- 2-POLE Y DC LUMINANCE RED LP PRE- DATA LP POST- X2 CLAMP OUTPUT FILTER DELAY LINE FILTER COMPOSITE NTSC/PAL X2 RGB-TO-YUV U OUTPUT DC 4-POLE U GREEN ENCODING CLAMP LPF CLAMP MATRIX BALANCED 4-POLE CHROMINANCE X2 MODULATORS LPF OUTPUT V DC 4-POLE V BLUE CLAMP LPF CLAMP BURST REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: (Unless otherwise noted, V = +5, T = +258C, using FSC synchronous clock. All loads are S A 150 V 6 5% at the IC pins. Outputs are measured at the 75 V reverse terminated load.) AD724SPECIFICATIONS Parameter Conditions Min Typ Max Units SIGNAL INPUTS (RIN, GIN, BIN) Input Amplitude Full Scale 714 mV p-p 1 Black Level 0.8 V 2 Input Resistance RIN, GIN, BIN 1 MW Input Capacitance 5pF LOGIC INPUTS (HSYNC, VSYNC, FIN, ENCD, STND, SELECT) CMOS Logic Levels Logic LO Input Voltage 1V Logic HI Input Voltage 2V Logic LO Input Current (DC) <1 m A Logic HI Input Current (DC) <1 m A 3 VIDEO OUTPUTS Luminance (LUMA) Roll-Off 5 MHz NTSC 7 dB PAL 6 dB Gain Error 15 3 +15 % Nonlinearity 0.3 % Sync Level NTSC 243 286 329 mV PAL 300 mV DC Black Level 1.3 V Chrominance (CRMA) Bandwidth NTSC 3.6 MHz PAL 4.4 MHz Color Burst Amplitude NTSC 170 249 330 mV p-p PAL 288 mV 4 5% Color Signal to Burst Ratio Error Color Burst Width NTSC 2.51 m s PAL 2.28 m s 5 3 Degrees Phase Error DC Black Level 2.0 V Chroma Feedthrough R, G, B = 0 15 40 mV p-p Composite (COMP) Absolute Gain Error With Respect to Luma 5 15 % Differential Gain With Respect to Chroma 0.5 % Differential Phase With Respect to Chroma 2.0 Degrees DC Black Level 1.5 V Chroma/Luma Time Alignment 0ns POWER SUPPLIES Recommended Supply Range Single Supply +4.75 +5.25 V 6 Quiescent CurrentEncode Mode 33 42 mA Quiescent CurrentPower Down 1 mA NOTES 1 R, G, and B signals are inputted via an external ac coupling capacitor. 2 Except during dc restore period (back porch clamp). 3 All outputs measured at a 75 W reverse-terminated load ac voltages at the IC output pins are twice those specified here. 4 Ratio of chroma amplitude to burst amplitude, difference from ideal. 5 Difference between ideal color-bar phases and the actual values. 6 Driving the logic inputs with VOH < 4 V will increase static supply current approximately 150 m A per input. Specifications are subject to change without notice. 2 REV. B

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8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits Digital.
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