Low Noise, High Throughput a 24-Bit Sigma-Delta ADC AD7731 FEATURES GENERAL DESCRIPTION 24-Bit Sigma-Delta ADC The AD7731 is a complete analog front-end for process control 16 Bits p-p Resolution at 800 Hz Output Rate applications. The device has a proprietary programmable gain Programmable Output Rates up to 6.4 kHz front end that allows it to accept a range of input signal ranges, Programmable Gain Front End including low level signals, directly from a transducer. The sigma- 60.0015% Nonlinearity delta architecture of the part consists of an analog modulator Buffered Differential Inputs and a low pass programmable digital filter, allowing adjustment Programmable Filter Cutoffs of filter cutoff, output rate and settling time. FASTStep* Mode for Channel Sequencing The part features three buffered differential programmable gain Single Supply Operation analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part oper- APPLICATIONS ates from a single +5 V supply and accepts seven unipolar ana- Process Control log input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV, PLCs/DCS +320 mV, +640 mV and +1.28 V, and seven bipolar ranges: Industrial Instrumentation 20 mV, 40 mV, 80 mV, 160 mV, 320 mV, 640 mV and 1.28 V. The peak-to-peak resolution achievable directly from the part is 16 bits at an 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a perfor- mance level of 13 bits of peak-to-peak resolution. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/C and a gain drift of less than 2 ppm/C. The part is available in a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM REF IN() AV DV REF IN(+) DD DD AD7731 NC AV DD STANDBY AIN1 SIGMA-DELTA A/D CONVERTER 100nA BUFFER AIN2 SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL AIN3 MODULATOR FILTER PGA MUX AIN4 100nA AIN5 CLOCK MCLK IN GENERATION AGND SERIAL INTERFACE AIN6 MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CS CALIBRATION MICROCONTROLLER DIN DOUT AGND DGND POL RDY RESET *FASTStep is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: (AV = +5 V, DV = +3 V or +5 V REF IN(+) = +2.5 V REF IN() = AGND AGND = DD DD DGND = 0 V f = 4.9152 MHz. All specifications T to T unless otherwise noted.) AD7731SPECIFICATIONS CLK IN MIN MAX 1 Parameter B Version Units Conditions/Comments STATIC PERFORMANCE (CHP = 0) 2 3 No Missing Codes 24 Bits min SKIP = 0 2 Output Noise and Update Rates See Tables I and II Integral Nonlinearity 15 ppm of FSR max 2 Offset Error See Note 4 Offset Error and Offset Drift Refer to Both 2 Offset Drift vs. Temperature 0.5 V/C typ Input Range = 20 mV, 40 mV, 80 mV, 160 mV 1/2/5 V/C typ Input Range = 320 mV/640 mV/1.28 V 5 Offset Drift vs. Time 2.5 V/1000 Hr 2, 6 Positive Full-Scale Error See Note 4 2, 7, 8 Positive Full-Scale Drift vs. Temp 0.6 V/C typ Input Range = 20 mV, 40 mV, 80 mV, 160 mV 1.5/3/6 V/C typ Input Range = 320 mV/640 mV/1.28 V 5 Positive Full-Scale Drift vs. Time 3 V/1000 Hr 2, 9 Gain Error See Note 4 2, 7, 10 Gain Drift vs. Temperature 2 ppm/C typ 5 Gain Drift vs. Time 10 ppm/1000 Hr 2 Bipolar Negative Full-Scale Error See Note 4 2, 7 Negative Full-Scale Drift vs. Temp 1 V/C typ 11 Power Supply Rejection 90 dB typ Input Range = 20 mV 11 Power Supply Rejection 60 dB typ Input Range = 1.28 V 11 Common-Mode Rejection (CMR) On AIN 95 dB typ At DC. Input Range = 20 mV On AIN 85 dB typ At DC. Input Range = 1.28 V On REF IN 120 dB typ 2 Analog Input DC Bias Current 60 nA max 2 Analog Input DC Bias Current Drift 150 pA/C typ 2 Analog Input DC Offset Current 30 nA max 2 Analog Input DC Offset Current Drift 100 pA/C typ 2 STATIC PERFORMANCE (CHP = 1) No Missing Codes 24 Bits min Output Noise and Update Rates See Tables III and IV Integral Nonlinearity 15 ppm of FSR max Offset Error See Note 4 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature 5 nV/C typ Unipolar Offset and Bipolar Zero Errors 5 Offset Drift vs. Time 25 nV/1000 Hr typ 6 Positive Full-Scale Error See Note 4 7, 8 Positive Full-Scale Drift vs. Temp 2 ppm of FS/C max 5 Positive Full-Scale Drift vs. Time 10 ppm of FS/1000 Hr 9 Gain Error See Note 4 7, 10 Gain Drift vs. Temperature 2 ppm/C max 5 Gain Drift vs. Time 10 ppm/1000 Hr Bipolar Negative Full-Scale Error See Note 4 Negative Full-Scale Drift vs. Temp 2 ppm of FS/C max 11 Power Supply Rejection 110 dB typ Input Range = 20 mV 11 Power Supply Rejection 85 dB typ Input Range = 1.28 V 11 Common-Mode Rejection (CMR) On AIN 110 dB typ At DC. Input Range = 20 mV On AIN 85 dB typ At DC. Input Range = 1.28 V On REF IN 120 dB typ Analog Input DC Bias Current 50 nA max Analog Input DC Bias Current Drift 100 pA/C typ Analog Input DC Offset Current 10 nA max Analog Input DC Offset Current Drift 50 pA/C typ ANALOG INPUTS/REFERENCE INPUTS 2 Normal Mode 50 Hz/60 Hz Rejection 88 dB min 50 Hz/60 Hz 1 Hz. SKIP = 0 2 Common-Mode 50 Hz/60 Hz Rejection 120 dB min 50 Hz/60 Hz 1 Hz. SKIP = 0 Analog Inputs 12 Differential Input Voltage Ranges Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately 0 to +20 or 20 mV nom RN2, RN1, RN0 of Mode Register = 0, 0, 1 0 to +40 or 40 mV nom RN2, RN1, RN0 of Mode Register = 0, 1, 0 0 to +80 or 80 mV nom RN2, RN1, RN0 of Mode Register = 0, 1, 1 0 to +160 or 160 mV nom RN2, RN1, RN0 of Mode Register = 1, 0, 0 0 to +320 or 320 mV nom RN2, RN1, RN0 of Mode Register = 1, 0, 1 0 to +640 or 640 mV nom RN2, RN1, RN0 of Mode Register = 1, 1, 0 0 to +1.28 or 1.28 V nom RN2, RN1, RN0 of Mode Register = 1, 1, 1 2 REV. 0