625 kSPS, 24-Bit, 109 dB Sigma-Delta ADC With On-Chip Buffer Data Sheet AD7762 FEATURES FUNCTIONAL BLOCK DIAGRAM V V 120 dB dynamic range at 78 kHz output data rate IN IN+ 109 dB dynamic range at 625 kHz output data rate 112 dB SNR at 78 kHz output data rate MULTIBIT AV DD1 DIFF - MODULATOR AV 106 dB SNR at 625 kHz output data rate DD2 AV DD3 625 kHz maximum fully filtered output word rate V REF+ AV RECONSTRUCTION DD4 BUF Programmable over-sampling rate (32 to 256) DECAPA/B Fully differential modulator input R BIAS On-chip differential amplifier for signal buffering AD7762 PROGRAMMABLE AGND DECIMATION Low-pass finite impulse response (FIR) filter with default or V DRIVE user-programmable coefficients MCLK CONTROL LOGIC DV DD Overrange alert bit I/O SYNC DGND OFFSET AND GAIN Digital offset and gain correction registers REGISTERS FIR FILTER RESET ENGINE Filter bypass modes Low power and power-down modes Synchronization of multiple devices via SYNC pin CS RD/WR DRDY DB0 TO DB15 Figure 1. APPLICATIONS Data acquisition systems Vibration analysis Instrumentation GENERAL DESCRIPTION The AD7762 is a high performance, 24-bit - analog-to- coefficients. The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency digital converter (ADC). It combines wide input bandwidth and high speed with the benefits of - conversion with a and the configuration registers of the AD7762. performance of 106 dB SNR at 625 kSPS, making it ideal for The reference voltage supplied to the AD7762 determines the high speed data acquisition. Wide dynamic range combined analog input range. With a 4 V reference, the analog input range with significantly reduced antialiasing requirements simplify is 3.2 V differential biased around a common mode of 2 V. the design process. An integrated buffer to drive the reference, This common-mode biasing can be achieved using the on-chip a differential amplifier for signal buffering and level shifting, an differential amplifier, further reducing the external signal overrange flag, internal gain and offset registers, and a low-pass conditioning requirements. digital FIR filter make the AD7762 a compact, highly integrated data acquisition device requiring minimal peripheral com- The AD7762 is available in an exposed paddle, 64-lead TQFP ponent selection. In addition, the device offers programmable and is specified over the industrial temperature range from decimation rates, and the digital FIR filter can be adjusted if 40C to +85C. the default characteristics are not appropriate to the application. The AD7762 is ideal for applications demanding high SNR Table 1. Related Devices without a complex front end signal processing design. Part No. Description AD7760 24-bit, 2.5 MSPS, 100 dB -, parallel interface The differential input is sampled at up to 40 MSPS by an analog AD7763 24-bit, 625 kSPS, 109 dB -, serial interface modulator. The modulator output is processed by a series of low- pass filters, the final filter having default or user-programmable Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20052014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 05477-001AD7762 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driving the AD7762 ....................................................................... 16 Applications ....................................................................................... 1 Using the AD7762 ...................................................................... 17 Functional Block Diagram .............................................................. 1 Bias Resistor Selection ............................................................... 17 General Description ......................................................................... 1 Decoupling and Layout Recommendations................................ 18 Revision History ............................................................................... 2 Supply Decoupling ..................................................................... 19 Specifications ..................................................................................... 3 Additional Decoupling .............................................................. 19 Timing Specifications ....................................................................... 5 Reference Voltage Filtering ....................................................... 19 Timing Diagrams .......................................................................... 5 Differential Amplifier Components ........................................ 19 Absolute Maximum Ratings ............................................................ 6 Layout Considerations ............................................................... 19 ESD Caution .................................................................................. 6 Programmable FIR Filter ............................................................... 20 Pin Configuration and Function Descriptions ............................. 7 Downloading a User-Defined Filter ............................................ 21 Terminology ...................................................................................... 9 Example Filter Download ......................................................... 21 Typical Performance Characteristics ........................................... 10 AD7762 Registers ........................................................................... 23 Theory of Operation ...................................................................... 13 Control Register 1Reg 0x0001 .............................................. 23 AD7762 Interface ............................................................................ 14 Control Register 2Address 0x0002 ...................................... 23 Reading Data ............................................................................... 14 Status Register (Read Only) ...................................................... 24 Sharing the Parallel Bus ............................................................. 14 Offset RegisterAddress 0x0003 ............................................. 24 Writing to the AD7762 .............................................................. 14 Gain RegisterAddress 0x0004 ............................................... 24 Reading Status and Other Registers ......................................... 14 Overrange RegisterAddress 0x0005 ..................................... 24 Clocking the AD7762 ................................................................ 15 Outline Dimensions ....................................................................... 25 Example 1 .................................................................................... 15 Ordering Guide .......................................................................... 25 Example 2 .................................................................................... 15 REVISION HISTORY 1/14Rev. 0 to Rev. A Added Exposed Pad Notation, Figure 4 and Table 5...7 Change to Figure 3120 Updated Outline Dimensions25 8/05Revision 0: Initial Version Rev. A Page 2 of 28