5 MHz400 MHz 100 dB High Precision a Limiting-Logarithmic Amplifier AD8306 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete, Fully Calibrated Log-Limiting IF Amplifier 100 dB Dynamic Range: 91 dBV to +9 dBV SIX STAGES TOTAL GAIN 72dB TYP GAIN 18dB Stable RSSI Scaling Over Temperature and Supplies: INHI LMHI 20 mV/dB Slope, 95 dBm Intercept 12dB 12dB 12dB LIM INLO LMLO 60.4 dB RSSI Linearity up to 200 MHz BIAS Programmable Limiter Gain and Output Current LADR ATTEN LMDR CTRL 4 3 DET DET DET DET Differential Outputs to 10 mA, 2.4 V p-p Overall Gain 90 dB, Bandwidth 400 MHz IV VLOG Constant Phase (Typical 656 ps Delay Skew) TEN DETECTORS SPACED 12dB FLTR Single Supply of +2.7 V to +6.5 V at 16 mA Typical Fully Differential Inputs, R = 1 kV, C = 2.5 pF IN IN GAIN BAND-GAP SLOPE INTERCEPT ENBL BIAS REFERENCE BIAS TEMP COMP 500 ns Power-Up Time, <1 mA Sleep Current APPLICATIONS Receivers for Frequency and Phase Modulation Very Wide Range IF and RF Power Measurement Receiver Signal Strength Indication (RSSI) Low Cost Radar and Sonar Signal Processing Instrumentation: Network and Spectrum Analyzers The overall dynamic range for this combination extends from PRODUCT DESCRIPTION 91 dBV (78 dBm at the 50 W level) to a maximum permissible The AD8306 is a complete IF limiting amplifier, providing both value of +9 dBV, using a balanced drive of antiphase inputs each of an accurate logarithmic (decibel) measure of the input signal 2 V in amplitude, which would correspond to a sine wave power (the RSSI function) over a dynamic range of 100 dB, and a of +22 dBm if the differential input were terminated in 50 W . programmable limiter output, useful from 5 MHz to 400 MHz. Through laser trimming, the slope of the RSSI output is closely It is easy to use, requiring few external components. A single controlled to 20 mV/dB, while the intercept is set to 108 dBV supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre- (95 dBm re 50 W ). These scaling parameters are determined sponding to a power consumption of under 50 mW at 3 V, plus by a band-gap voltage reference and are substantially indepen- the limiter bias current, determined by the application and typi- dent of temperature and supply. The logarithmic law conform- cally 2 mA, providing a limiter gain of 90 dB when using 200 W ance is typically within 0.4 dB over the central 80 dB of this loads. A CMOS-compatible control interface can enable the range at any frequency between 10 MHz and 200 MHz, and is AD8306 within about 500 ns and disable it to a standby current degraded only slightly at 400 MHz. of under 1 m A. The RSSI response time is nominally 73 ns (10%90%). The The six cascaded amplifier/limiter cells in the main path have a averaging time may be increased without limit by the addition of small signal gain of 12.04 dB ( 4), with a 3 dB bandwidth of an external capacitor. The full output of 2.34 V at the maximum 850 MHz, providing a total gain of 72 dB. The programmable input of +9 dBV can drive any resistive load down to 50 W and output stage provides a further 18 dB of gain. The input is fully this interface remains stable with any value of capacitance on differential and presents a moderately high impedance (1 kW in the output. parallel with 2.5 pF). The input-referred noise-spectral-density, The AD8306 is fabricated on an advanced complementary when driven from a terminated 50 W , source is 1.28 nV/ Hz, bipolar process using silicon-on-insulator isolation techniques equivalent to a noise figure of 3 dB. The sensitivity of the and is available in the industrial temperature range of 40 C to AD8306 can be raised by using an input matching network. +85 C, in a 16-lead narrow body SO package. The AD8306 is Each of the main gain cells includes a full-wave detector. An also available for the full military temperature range of 55 C to additional four detectors, driven by a broadband attenuator, are +125 C, in a 16-lead side-brazed ceramic DIP. used to extend the top end of the dynamic range by over 48 dB. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: (V = +5 V, T = +258C, f = 10 MHz, unless otherwise noted) AD8306SPECIFICATIONS S A 1 1 Parameter Conditions Min Typ Max Units INPUT STAGE (Inputs INHI, INLO) 2 Maximum Input Differential Drive, p-p 3.5 4V +9 dBV Equivalent Power in 50 W Terminated in 52.3 W iR +22 dBm IN Noise Floor Terminated 50 W Source 1.28 nV/ Hz Equivalent Power in 50 W 400 MHz Bandwidth 78 dBm Input Resistance From INHI to INLO 800 1000 1200 W Input Capacitance From INHI to INLO 2.5 pF DC Bias Voltage Either Input 1.725 V LIMITING AMPLIFIER (Outputs LMHI, LMLO) Usable Frequency Range 5 400 MHz At Limiter Output R = R = 50 W , to 10 dB Point 585 MHz LOAD LIM Phase Variation at 100 MHz Over Input Range 73 dBV to 3 dBV 2 Degrees Limiter Output Current Nominally 400 mV/R 0110 mA LIM Versus Temperature 40 C T +85 C 0.008 %/ C A 3 Input Range 78 +9 dBV Maximum Output Voltage At Either LMHI or LMLO, wrt VPS2 1 1.25 V Rise/Fall Time (10%90%) R = 50 W , 40 W R 400 W 0.6 ns LOAD LIM LOGARITHMIC AMPLIFIER (Output VLOG) 3 dB Error Dynamic Range From Noise Floor to Maximum Input 100 dB 4 Transfer Slope f = 10 MHz 19.5 20 20.5 mV/dB f = 100 MHz 19.6 mV/dB Over Temperature 40 C < T < +85 C 19.3 20 20.7 mV/dB A 4 Intercept (Log Offset) f = 10 MHz 109.5 108 106.5 dBV f = 100 MHz 108.4 dBV Over Temperature 40 C T +85 C 111 108 105 dBV A Temperature Sensitivity 0.009 dB/ C Linearity Error (Ripple) Input from 80 dBV to +0 dBV 0.4 dB Output Voltage Input = 91 dBV, V = +5 V, +2.7 V 0.34 V S Input = +9 dBV, V = +5 V 2.34 2.75 V S Input = 3 dBV, V = +3 V 2.10 V S Minimum Load Resistance, R 40 50 W L Maximum Sink Current To Ground 0.75 1.0 1.25 mA Output Resistance 0.3 W Small-Signal Bandwidth 3.5 MHz Output Settling Time to 2% Large Scale Input, +3 dBV, R 50 W , C 100 pF 120 220 ns L L Rise/Fall Time (10%90%) Large Scale Input, +3 dBV, R 50 W , C 100 pF 73 100 ns L L POWER INTERFACES Supply Voltage, V 2.7 5 6.5 V S Quiescent Current Zero-Signal, LMDR Open 13 16 20 mA Over Temperature 40 C < T < +85 C 111623 mA A Disable Current 40 C < T < +85 C 0.01 4 m A A Additional Bias for Limiter R = 400 W (See Text) 2.0 2.25 mA LIM Logic Level to Enable Power HI Condition, 40 C < T < +85 C 2.7 V V A S Input Current when HI 3 V at ENBL, 40 C < T < +85 C4060 m A A Logic Level to Disable Power LO Condition, 40 C < T < +85 C 0.5 1 V A TRANSISTOR COUNT of Transistors 207 207 NOTES 1 Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2 The input level is specified in dBV since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of 1 V rms. A power level of 0 dBm (1 mW) in a 50 W termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50 W termination, dBV values can be converted into dBm by adding a fixed offset of +13 to the dBV rms value. 3 Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below 78 dBV (65 dBm, re 50 W ). 4 Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17. Specifications subject to change without notice. 2 REV. A