DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter Data Sheet AD8339 FEATURES FUNCTIONAL BLOCK DIAGRAM RF1N RF1P Quad integrated I/Q demodulator AD8339 16 phase select on each output (22.5 per step) Quadrature demodulation accuracy I1OP RSTS Phase accuracy: 1 SCLK SERIAL Amplitude imbalance: 0.05 dB SDI Q1OP INTERFACE SDO Bandwidth CSB I2OP 4LO: LF to 200 MHz RF2P RF: LF to 50 MHz RF2N Q2OP Baseband: determined by external filtering 0 4LOP Output dynamic range: 160 dB/Hz 4 90 4LON I3OP LO drive: >0 dBm (50 ), single-ended sine wave RF3P Supply: 5 V RF3N Q3OP Power consumption: 73 mW/channel (290 mW total) VPOS Power-down via SPI (each channel and complete chip) BIAS I4OP VNEG APPLICATIONS Q4OP Medical imaging (CW ultrasound beamforming) Phased array systems RF4N RF4P Radar Figure 1. Adaptive antennas Communication receivers GENERAL DESCRIPTION 1 The AD8339 is a quad I/Q demodulator configured to be The mixer outputs are in current form for convenient summa- driven by a low noise preamplifier with differential outputs. It is tion. The independent I and Q mixer output currents are summed optimized for the LNA in the AD8332/AD8334/AD8335 family and converted to a voltage by a low noise, high dynamic range, of VGAs. The part consists of four identical I/Q demodulators current-to-voltage (I-V) transimpedance amplifier, such as the with a 4 local oscillator (LO) input that divides the signal and AD8021 or the AD829. Following the current summation, the generates the necessary 0 and 90 phases of the internal LO combined signal is applied to a high resolution analog-to-digital that drive the mixers. The four I/Q demodulators can be used converter (ADC), such as the AD7665 (16-bit, 570 kSPS). independently of each other (assuming that a common LO is An SPI-compatible serial interface port is provided to easily acceptable) because each has a separate RF input. program the phase of each channel the interface allows daisy Continuous wave (CW) analog beamforming (ABF) and I/Q chaining by shifting the data through each chip from SDI to SDO. demodulation are combined in a single 40-lead, ultracompact The SPI also allows for power-down of each individual channel chip scale device, making the AD8339 particularly applicable in and the complete chip. During power-down, the serial interface high density ultrasound scanners. In an ABF system, time remains active so that the device can be programmed again. domain coherency is achieved following the appropriate phase The dynamic range is typically 160 dB/Hz at the I and Q alignment and summation of multiple receiver channels. A reset outputs. The AD8339 is available in a 6 mm 6 mm, 40-lead pin synchronizes multiple ICs to start each LO divider in the LFCSP and is specified over the industrial temperature range of same quadrant. Sixteen programmable 22.5 phase increments 40C to +85C. are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45, the user can phase align Channel 2 with Channel 1 by choosing the appropriate phase select code. 1 Protected by U.S. Patent Number 7,760,833. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 06587-001AD8339 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Dynamic Range and Noise ........................................................ 19 Applications ....................................................................................... 1 Multichannel Summation ......................................................... 20 Functional Block Diagram .............................................................. 1 Serial Interface ................................................................................ 23 General Description ......................................................................... 1 ENBL Bits .................................................................................... 23 Revision History ............................................................................... 2 Applications Information .............................................................. 24 Specifications ..................................................................................... 3 Logic Inputs and Interfaces ....................................................... 24 Absolute Maximum Ratings ............................................................ 5 Reset Input .................................................................................. 24 ESD Caution .................................................................................. 5 LO Input ...................................................................................... 24 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ............................................................................ 25 Equivalent Input Circuits ................................................................ 7 Connections to the Board ......................................................... 26 Typical Performance Characteristics ............................................. 8 Test Configurations .................................................................... 26 Test Circuits ..................................................................................... 14 AD8339-EVALZ Artwork ......................................................... 33 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 35 Quadrature Generation ............................................................. 19 Ordering Guide .......................................................................... 35 I/Q Demodulator and Phase Shifter ........................................ 19 REVISION HISTORY 7/12Rev. A to Rev. B Changes to Evaluation Board Section and Figure 58 ................ 25 Changes to Connections to the Board Section and Table 5 ...... 26 Changes to Figure 1 and General Description Section ................ 1 Changes to Figure 60 ...................................................................... 27 2/09Rev. 0 to Rev. A Changes to Figure 61 ...................................................................... 28 Change to Figure 1 ........................................................................... 1 Changes to Table 7 .......................................................................... 29 Change to Table 2 ............................................................................. 5 Changes to Figure 63 ...................................................................... 30 Added Exposed Pad Notation to Figure 2 Changes to Figure 64 ...................................................................... 31 Changes to Table 3 ............................................................................ 6 Changes to Figure 65 ...................................................................... 32 Changes to Figure 3 Added Figure 4 Changes to Figure 66 and Figure 67............................................. 33 Renumbered Sequentially ................................................................ 7 Changes to Figure 68 and Figure 69............................................. 34 Changes to Theory of Operation Section .................................... 18 Deleted Table 8 ................................................................................ 35 Changes to Dynamic Range and Noise Section, ........................ 20 Updated Outline Dimensions ....................................................... 35 Changes to Channel Summing Section ....................................... 21 Added Figure 55 .............................................................................. 22 8/07Revision 0: Initial Version Changes to Serial Interface Section, ENBL Bits Section, Figure 56, and Figure 57 ................................................................ 23 Rev. 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