Data Sheet AD9081 MxFE Quad, 16-Bit, 12 GSPS RF DAC and Quad, 12-Bit, 4 GSPS RF ADC FEATURES Low latency loopback mode (receive datapath data can be routed to the transmit datapaths) Flexible, reconfigurable common platform design ADC clock driver with selectable divide ratios 4 DACs and 4 ADCs (4D4A) Power amplifier downstream protection circuitry Supports single, dual, and quad band On-chip temperature monitoring unit Datapaths and DSP blocks are fully bypassable Flexible GPIO pins DAC to ADC sample rate ratios of 1, 2, 3, and 4 TDD power savings option and sharing ADCs On-chip PLL with multichip synchronization SERDES JESD204B/JESD204C interface, 16 lanes up to External RFCLK input option for off-chip PLL 24.75 Gbps Maximum DAC sample rate up to 12 GSPS 8 lanes JESD204B/C transmitter (JTx) and 8 lanes Maximum data rate up to 12 GSPS using JESD204C JESD204B/C receiver (JRx) Useable analog bandwidth to 8 GHz JESD204B compliance with the maximum 15.5 Gbps Maximum ADC sample rate up to 4 GSPS JESD204C compliance with the maximum 24.75 Gbps Maximum data rate up to 4 GSPS using JESD204C Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 7.5 GHz analog input full power bandwidth (3 dB) 15 mm 15 mm, 324-ball BGA with 0.8 mm pitch ADC ac performance at 4 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.4 V p-p APPLICATIONS Noise density: 147.5 dBFS/Hz Wireless communications infrastructure Noise figure: 26.8 dB Microwave point to point, E-band, and 5G mmWave HD2: 67 dBFS Broadband communications systems HD3: 73 dBFS DOCSIS 3.1 and 4.0 CMTS Worst other (excluding HD2 and HD3): 79 dBFS at 2.7 GHz Phased array radar and electronic warfare DAC ac performance at 12 GSPS Electronic test and measurement systems Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (7 dBFS per tone): 78.9 dBc GENERAL DESCRIPTION NSD, single-tone at 3.7 GHz: 155.1 dBc/Hz The AD9081 mixed signal front end (MxFE ) is a highly integrated SFDR, single-tone at 3.7 GHz: 70 dBc device with four 16-bit, 12 GSPS maximum sample rate, RF digital- Versatile digital features to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, Configurable or bypassable DDCs and DUCs RF analog-to-digital converter (ADC) cores. The AD9081 is well 8 fine complex DUCs and 4 coarse complex DUCs suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The 8 fine complex DDCs and 4 coarse complex DDCs device features eight transmit and eight receive lanes that support 48-bit NCO per DUC or DDC 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B stand- Programmable 192-tap PFIR filter for receive equalization ards. The device also has an on-chip clock multiplier, and a digital Supports 4 different profile settings loaded via GPIO signal processing (DSP) capability targeted at either wideband or Programmable delay per datapath multiband direct to RF applications. The DSP datapaths can be Receive AGC support bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features Fast detect with low latency for fast AGC control low latency loopback and frequency hopping modes targeted at Signal monitor for slow AGC control phase array radar system and electronic warfare applications. Two Transmit DPD support models for the AD9081 are offered. The 4D4AC model supports the Fine DUC channel gain control and delay adjust full instantaneous channel bandwidth, whereas the 4D4AB model Coarse DDC delay adjust for DPD observation path supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instanta- Auxiliary features neous bandwidth at startup. See the Ordering Guide for more Fast frequency hopping and direct digital synthesis (DDS) information. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliableas i. However, no responsibility is assumed by Analog DOCUMENT FEEDBACK Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and TECHNICAL SUPPORT registered trademarks are the property of their respective owners.Data Sheet AD9081 TABLE OF CONTENTS Features................................................................ 1 CMOS Pin Specifications................................. 13 Applications........................................................... 1 DAC AC Specifications.....................................13 General Description...............................................1 ADC AC Specifications.....................................16 Functional Block Diagram......................................3 Timing Specifications....................................... 19 Specifications........................................................ 4 Absolute Maximum Ratings.................................21 Recommended Operating Conditions................ 4 Thermal Resistance......................................... 21 Power Consumption...........................................4 ESD Caution.....................................................21 DAC DC Specifications...................................... 5 Pin Configuration and Function Descriptions...... 22 ADC DC Specifications...................................... 6 Typical Performance Characteristics...................27 Clock Inputs and Outputs...................................7 DAC..................................................................27 Clock Input and Phase-Locked Loop (PLL) ADC: 4 GSPS...................................................32 Frequency Specifications................................. 7 ADC: 3 GSPS...................................................39 DAC Sample Rate Specifications.......................8 Theory of Operation.............................................43 ADC Sample Rate Specifications.......................9 Applications Information...................................... 44 Input Data Rate Specifications.........................10 Outline Dimensions............................................. 45 NCO Frequency Specifications........................ 11 Ordering Guide.................................................45 JESD204B and JESD204C Interface Evaluation Boards............................................ 45 Electrical and Speed Specifications............... 11 REVISION HISTORY 4/2021Revision 0: Initial Version analog.com Rev. 0 2 of 45