16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter Data Sheet AD9083 FEATURES APPLICATIONS 1.0 V and 1.8 V supply operation Millimeter wave imaging 125 MHz usable analog input bandwidth Electronic beam forming and phased arrays Sample rate up to 2 GSPS Multichannel wideband receivers Noise spectral density in 100 MHz bandwidth = Electronic support measures 145 dBFS/Hz, 2.0 GSPS encode PRODUCT HIGHLIGHTS SNR = 66 dBFS in 100 MHz bandwidth, 2.0 GSPS encode 1. Continuous time, - analog-to-digital converters (ADCs) SNR = 82 dBFS in 15.625 MHz bandwidth, 2.0 GSPS encode support signal bandwidths of up to 125 MHz with low SFDR = 60 dBc in 100 MHz bandwidth, 2.0 GSPS encode power and minimal filtering. SFDR = 80 dBc in 15.625 MHz bandwidth, 2.0 GSPS encode 2. Integrated digital processing blocks reduce data payload 90 mW total power per channel at 2.0 GSPS (default settings) and lower overall system cost. Flexible input range: 0.5 V p-p to 2 V p-p differential 3. Configurable JESD204B interface reduces printed circuit 90 dB channel crosstalk, 2.0 GSPS encode board (PCB) complexity. Digital processor 4. Flexible power-down options. CIC decimation filter 5. SPI interface controls various product features and Programmable DDC functions to meet specific system requirements. Data gating 6. Small, 9 mm 9 mm, 100-ball CSP BGA package, simple JESD204B Subclass 1 encoded outputs interface, and integrated digital processing save PCB space. Supports up to 16 Gbps/lane Flexible sample data processing Flexible JESD204B lane configurations Large signal dither Serial port control FUNCTIONAL BLOCK DIAGRAM AVDD AVDD1P8 DVDD DVDD1P8 (1V) (1.8V) (1V) (1.8V) AD9083 NCO NCO NCO 0 1 2 DECIMATE GAIN BY J VIN1+ TO MIXER VIN16+ AVERAGING AND ADC DECIMATION FILTER SERDOUT0 VIN1 TO CIC DECIMATOR JESD204B VIN16 SERDOUT1 OUTPUTS SERDOUT2 SERDOUT3 AVERAGING AND MIXER GAIN DECIMATION FILTER AVERAGING AND MIXER GAIN SYNCINB DECIMATION FILTER 16 CHANNELS CLK CSB PLL, SPI AND CONTROL SYSREF JESD204B SUBCLASS1 CONTROL, SCLK REGISTERS AND CLOCK DISTRIBUTION TRIG SDIO AGND DGND PD/STBY Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2021 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 22923-001AD9083 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Nonburst Mode Datapath ......................................................... 37 Applications ...................................................................................... 1 Burst Mode Datapath ................................................................ 41 Product Highlights ........................................................................... 1 Averaging Filters ........................................................................ 42 Functional Block Diagram .............................................................. 1 Mixers .......................................................................................... 43 Revision History ............................................................................... 2 NCO FTW Description ............................................................. 43 General Description ......................................................................... 3 Digital Outputs ............................................................................... 45 Specifications .................................................................................... 4 JESD204B Overview .................................................................. 45 DC Specifications ......................................................................... 4 Functional Overview ................................................................. 46 AC Specifications ......................................................................... 5 JESD204B Link Establishment ................................................. 46 Digital Specifications ................................................................. 10 Physical Layer (Driver) Outputs .............................................. 48 Switching Specifications ............................................................ 11 Setting Up the AD9083 Digital Interface .................................... 49 Timing Specifications ................................................................ 12 JESD204B Transport Layer Settings ........................................ 49 Absolute Maximum Ratings ......................................................... 13 Deterministic Latency ............................................................... 51 Thermal Resistance .................................................................... 13 Multichip Synchronization ....................................................... 51 ESD Caution................................................................................ 13 Sampled SYSREF Mode ............................................................ 51 Pin Configuration and Function Descriptions .......................... 14 Serial Port Interface (SPI) ............................................................. 53 Typical Performance Characteristics ........................................... 17 Configuration Using the SPI .................................................... 53 Equivalent Circuits ......................................................................... 25 Hardware Interface .................................................................... 53 Terminology .................................................................................... 27 Programming Guide ...................................................................... 54 Theory of Operation ...................................................................... 28 Programming Sequence ............................................................ 54 ADC Architecture ...................................................................... 28 Memory Map .................................................................................. 60 Low-Pass, CTSD ADC Overview ............................................. 29 Logic Levels ................................................................................. 60 Low-Pass - ADC .................................................................... 29 Memory Map Register Details ...................................................... 61 Analog Inputs ............................................................................. 30 Applications Information ............................................................. 90 Clock Inputs ................................................................................ 32 Evaluation Board Information ................................................. 90 Power Modes .............................................................................. 33 Power Delivery Network ........................................................... 90 Temperature Diode .................................................................... 33 Layout Guidelines ...................................................................... 90 Digital Signal Processing Overview ......................................... 33 Outline Dimensions ....................................................................... 93 Signal Processing Tile .................................................................... 35 Ordering Guide .............................................................................. 93 Cascaded Integrator Comb (CIC) Filter ................................. 36 REVISION HISTORY 1/2021Revision 0: Initial Version Rev. 0 Page 2 of 93