DC to 9 GHz Vector Signal Generator Data Sheet AD9166 form generation without the need for external bias tees or similar FEATURES circuitry, which makes the AD9166 uniquely suited for the most DC-coupled, 50 matched output demanding high speed ultrawideband RF transmit applications. Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in The various filter stages enable the AD9166 to be configured for 2 NRZ mode lower data rates, while maintaining higher DAC clock rates to Wide analog bandwidth ease the filtering requirements and reduce the overall system size, DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) weight, and power. 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) The data interface receiver consists of up to eight JESD204B DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) SERDES lanes, each capable of carrying up to 12.5 Gbps. To Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC enable maximum flexibility, the receiver is fully configurable update rate) according to the data rate, number of SERDES lanes, and lane Bypassable datapath interpolation mapping required by the JESD204B transmitter. 2, 3, 4, 6, 8, 12, 16, 24 In 2 nonreturn-to-zero (NRZ) mode of operation (with FIR85 Instantaneous (complex) signal bandwidth enabled), the AD9166 can reconstruct RF carriers from true dc 2.25 GHz with device clock at 5 GHz (2 interpolation) to the edge of the third Nyquist zone, or an analog bandwidth of 1.8 GHz with device clock at 6 GHz (3 interpolation) true dc up to 9 GHz. Fast frequency hopping Integrated BiCMOS buffer amplifier In mix mode, the AD9166 can reconstruct RF carriers in the second and third Nyquist zones while consuming lower power APPLICATIONS and maintaining a performance comparable to 2 NRZ mode. Instrumentation: automated test equipment, electronic test In baseband modes, such as return-to-zero (RZ) and 1 NRZ, and measurement, arbitrary waveform generators the AD9166 is ideal to reconstruct RF carriers from true dc to Electronic warfare: radars, jammers the edge of the first Nyquist zone while consuming lower power Broadband communications systems compared to 2 NRZ mode. Local oscillator drivers The quadrature DDS block can be configured as a digital GENERAL DESCRIPTION upconverter to upconvert I/Q data samples to the desired 1 The AD9166 is a high performance, wideband, on-chip vector location across the spectrum, in all three Nyquist zones. signal generator composed of a high speed JESD204B serializer/ The DDS also consists of a bank of 32 numerically controlled deserializer (SERDES) interface, a flexible 16-bit digital datapath, a oscillators (NCOs), each with its own 32-bit phase accumulator. inphase/quadrature (I/Q) digital-to-analog converter (DAC) When combined with a 100 MHz serial peripheral interface (SPI), core, and an integrated differential to single-ended output the DDS allows a phase coherent FFH, with a phase settling buffer amplifier, matched to a 50 load up to 10 GHz. time as low as 300 ns. The DAC core is based on a quad-switch architecture, which is The AD9166 is configured using a common SPI interface that configurable to increase the effective DAC core update rate of monitors the status of all registers. The AD9166 is offered in a up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an 324-ball, 15 mm 15 mm, 0.8 mm pitch BGA ED package. analog output bandwidth of true dc to 9.0 GHz, typically. The digital datapath includes multiple interpolation filter stages, a PRODUCT HIGHLIGHTS direct digital synthesizer (DDS) block with multiple 1. High dynamic range and signal reconstruction bandwidth numerically controlled oscillators (NCOs) supporting fast supports RF signal synthesis of up to 9 GHz. frequency hopping (FFH), and additional FIR85 and inverse 2. Fully supports zero IF and other dc-coupled applications. sinc filter stages to allow flexible spectrum planning. 3. Up to an eight-lane JESD204B SERDES interface, with The differential to single-ended buffer eliminates the need for a various features to allow flexibility when interfacing to a wideband balun, and supports the full analog output bandwidth JESD204B transmitter. of the DAC core. DC coupling the output allows baseband wave- 1 Protected by U.S. Patents 6,842,132 and 7,796,971. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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AD9166 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Overview .................................................................. 29 Applications ....................................................................................... 1 Physical Layer ............................................................................. 31 General Description ......................................................................... 1 Data Link Layer .......................................................................... 34 Product Highlights ........................................................................... 1 Transport Layer .......................................................................... 42 Revision History ............................................................................... 2 JESD204B Test Modes ............................................................... 44 Functional Block Diagram .............................................................. 3 JESD204B Error Monitoring ..................................................... 46 Specificat ions ..................................................................................... 4 Hardware Considerations ......................................................... 48 DC Specifications ......................................................................... 4 Main Digital Datapath ................................................................... 49 Power Supply DC Specifications ................................................ 5 Data Format ................................................................................ 49 Device Input Clock Rate and DAC Update Rate Specifications Interpolation Filters ................................................................... 49 ......................................................................................................... 7 Digital Modulation ..................................................................... 52 JESD204B Interface Specifications ............................................. 8 Inverse Sinc ................................................................................. 55 Input Data Rate and Bandwidth Specifications ........................ 9 Downstream Protection ............................................................ 55 Pipeline Delay and Latency Uncertainty Specifications .......... 9 Datapath PRBS ........................................................................... 56 AC Specifications ........................................................................ 10 Datapath PRBS IRQ ................................................................... 56 CMOS Pin Specifications .......................................................... 11 Interrupt Request Operation ........................................................ 57 Timing Specifications ................................................................ 12 Interrupt Service Routine .......................................................... 57 Absolute Maximum Ratings .......................................................... 14 Applications Information .............................................................. 58 Reflow Profile .............................................................................. 14 Hardware Considerations ......................................................... 58 Thermal Management ............................................................... 14 Analog Interface Considerations .................................................. 61 Thermal Resistance .................................................................... 14 Analog Modes of Operation ..................................................... 61 ESD Caution ................................................................................ 14 Clock Input .................................................................................. 62 Pin Configuration and Function Descriptions ........................... 15 Shuffle Mode ............................................................................... 63 Typical Performance Characteristics ........................................... 18 Voltage Reference and Full-Scale Current (FSC) ................... 63 AC Performance (2 NRZ (FIR85) Mode) ............................. 18 Analog Output ............................................................................ 64 LTE Performance (2 NRZ (FIR85) Mode) ........................... 23 Temperature Sensors .................................................................. 65 802.11AC Performance (2 NRZ (FIR85) Mode) ................. 24 Start-Up Sequence .......................................................................... 67 Terminology .................................................................................... 25 Register Summary: DAC ............................................................... 70 Theory of Operation ...................................................................... 26 Register Details: DAC Register Map ............................................ 79 Serial Port Operation ..................................................................... 27 Register Summary: Amplifier ..................................................... 135 Data Format ................................................................................ 27 Register Details: Amplifier Register Map .................................. 136 Serial Port Pin Descriptions ...................................................... 27 Outline Dimensions ..................................................................... 138 Serial Port Options ..................................................................... 28 Ordering Guide ........................................................................ 138 JESD204B Serial Data Interface .................................................... 29 REVISION HISTORY 7/2020Revision 0: Initial Version Rev. 0 Page 2 of 138