12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter Data Sheet AD9625 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND 12-bit 2.5 GSPS ADC, no missing codes SFDR = 79 dBc, AIN up to 1 GHz at 1 dBFS, 2.5 GSPS REFERENCE DIGITAL INTERFACE AND CONTROL SERDOUT 0 SFDR = 77 dBc, AIN up to 1.8 GHz at 1 dBFS, 2.5 GSPS SERDOUT 1 VCM SERDOUT 2 SNR = 57.6 dBFS, AIN up to 1 GHz at 1 dBFS, 2.5 GSPS SERDOUT 3 SERDOUT 4 VIN+ DDC SNR = 57 dBFS, AIN up to 1.8 GHz at 1 dBFS, 2.5 GSPS ADC SERDOUT 5 f /8 OR f /16 CORE S S SERDOUT 6 VIN Noise spectral density = 149.5 dBFS/Hz at 2.5 GSPS SERDOUT 7 RBIAS EXT Differential analog input: 1.2 V p-p FD CMOS CONTROL DIGITAL Differential clock input REGISTERS RSTB INPUT/ OUTPUT IRQ 3.2 GHz analog input bandwidth, full power SYSREF High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS CLOCK LVDS SYNCINB MANAGEMENT DIGITAL CLK INPUT/ Subclass 1: 6.5 Gbps at 2.6 GSPS DIVCLK OUTPUT CMOS DIGITAL INPUT/OUTPUT Two independent decimate by 8 or decimate by 16 filters AD9625 with 10-bit NCOs Supply voltages: 1.3 V, 2.5 V SDIO SCLK CSB Serial port control Figure 1. Flexible digital output modes Built-in selectable digital test patterns Timestamp feature 15 Conversion error rate < 10 APPLICATIONS Spectrum analyzers Military communications Radar High performance digital storage oscilloscopes Active jamming/antijamming Electronic surveillance and countermeasures GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9625 is a 12-bit monolithic sampling analog-to-digital 1. High performance: exceptional SFDR in high sample rate converter (ADC) that operates at conversion rates of up to applications, direct RF sampling, and on-chip reference. 2.6 giga samples per second (GSPS). This product is designed 2. Flexible digital data output formats based on the JESD204B for sampling wide bandwidth analog signals up to the second specification. Nyquist zone. The combination of wide input bandwidth, high 3. Control path SPI interface port that supports various sampling rate, and excellent linearity of the AD9625 is ideally product features and functions, such as data formatting, suited for spectrum analyzers, data acquisition systems, and a gain, and offset calibration values. wide assortment of military electronics applications, such as radar and electronic countermeasures. The analog input, clock, and SYSREF signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of 40C to +85C, measured at the case. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com JESD204B INTERFACE 11814-001AD9625 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Numerically Controlled Oscillator .......................................... 33 Applications ....................................................................................... 1 High Bandwidth Decimator ..................................................... 33 Functional Block Diagram .............................................................. 1 Low Bandwidth Decimator ....................................................... 36 General Description ......................................................................... 1 Digital Outputs ............................................................................... 37 Product Highlights ........................................................................... 1 Introduction to the JESD204B Interface ................................. 37 Revision History ............................................................................... 3 Functional Overview ................................................................. 37 Specif icat ions ..................................................................................... 4 JESD204B Link Establishment ................................................. 39 DC Specifications ......................................................................... 4 Physical Layer Output ................................................................ 43 AC Specifications .......................................................................... 5 S crambler ..................................................................................... 43 Digital Specifications ................................................................... 6 Tail Bits ........................................................................................ 43 Switching Specifications .............................................................. 7 DDC Modes (Single and Dual) ................................................ 43 Timing Specifications .................................................................. 7 CheckSum ................................................................................... 44 Absolute Maximum Ratings ............................................................ 9 8-Bit/10-Bit Encoder Control ................................................... 44 Thermal Characteristics .............................................................. 9 Initial Lane Alignment Sequence (ILAS) ................................ 44 ESD Caution .................................................................................. 9 Lane Synchronization ................................................................ 45 Pin Configuration and Function Descriptions ........................... 10 JESD204B Application Layers .................................................. 48 Typical Performance Characteristics ........................................... 16 Frame Alignment Character Insertion .................................... 51 AD9625-2.0 ................................................................................. 17 Thermal Considerations ............................................................ 51 AD9625-2.5 ................................................................................. 20 Power Supply Considerations ................................................... 51 AD9625-2.6 ................................................................................. 24 Serial Port Interface (SPI) .............................................................. 52 Equivalent Test Circuits ................................................................. 27 Configuration Using the SPI ..................................................... 52 Theory of Operation ...................................................................... 28 Hardware Interface ..................................................................... 52 ADC Architecture ...................................................................... 28 Memory Map .................................................................................. 53 Fast Detect ................................................................................... 28 Reading the Memory Map Register ......................................... 53 Gain Threshold Operation ........................................................ 28 Memory Map Registers ............................................................. 53 Test Modes ................................................................................... 29 Applications Information .............................................................. 71 Analog Input Considerations ........................................................ 30 Design Guidelines ...................................................................... 71 Differential Input Configurations ............................................ 30 Power and Ground Recommendations ................................... 71 Using the ADA4961 ................................................................... 30 Clock Stability Considerations ................................................. 71 DC Coupling ............................................................................... 32 SPI Port ........................................................................................ 71 Clock Input Considerations ...................................................... 32 Outline Dimensions ....................................................................... 72 Digital Downconverters (DDC) ................................................... 33 Ordering Guide .......................................................................... 72 Frequency Synthesizer and Mixer ............................................ 33 Rev. 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