Octal Ultrasound AFE with Digital Demodulator Data Sheet AD9670 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, antialiasing filter, ADC, and digital The AD9670 is designed for low cost, low power, small size, and demodulator/decimator ease of use for medical ultrasound applications. It contains eight Low power channels of a VGA with an LNA, a CW harmonic rejection I/Q 150 mW per channel, time gain compensation (TGC) mode, demodulator with programmable phase rotation, an antialiasing 40 MSPS filter, an ADC, and a digital demodulator and decimator for data 62.5 mW per channel, continuous wave (CW) mode processing and bandwidth reduction. <30 mW in power-down mode Each channel features a maximum gain of up to 52 dB, a fully 10 mm 10 mm, 144-ball CSP BGA differential signal path, and an active input preamplifier termination. TGC channel, input referred noise voltage: 0.82 nV/Hz, The channel is optimized for high dynamic performance and maximum gain low power in applications where a small package size is critical. Flexible power-down modes The LNA has a single-ended-to-differential gain that is selectable Fast recovery from low power standby mode: <2 s through the serial port interface (SPI). Assuming a 15 MHz noise Low noise preamplifier (LNA) bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR Input noise voltage: 0.78 nV/Hz, gain = 21.6 dB is 94 dB. In CW Doppler mode, each LNA output drives an I/Q Programmable gain: 15.6 dB/17.9 dB/21.6 dB demodulator that has independently programmable phase 0.1 dB input compression point: 1.00 V p-p/0.75 V p-p/ rotation with 16 phase settings. 0.45 V p-p Flexible active input impedance matching Power-down of individual channels is supported to increase Variable gain amplifier (VGA) battery life for portable applications. Standby mode allows quick Attenuator range: 45 dB, linear-in-dB gain control power-up for power cycling. In CW Doppler operation, the Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB VGA, antialiasing filter, and ADC are powered down. The ADC Antialiasing filter contains several features designed to maximize flexibility and Programmable, second-order low-pass filter from 8 MHz to minimize system cost, such as a programmable clock, data 18 MHz or 13.5 MHz to 30 MHz and high-pass filter alignment, and programmable digital test pattern generation. Analog-to-digital converter (ADC) The digital test patterns include built-in fixed patterns, built-in Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS pseudorandom patterns, and custom user-defined test patterns Configurable serial low voltage differential signaling (LVDS) entered via the SPI. CW mode harmonic rejection I/Q demodulator Individual programmable phase rotation Dynamic range per channel: >160 dBFS/Hz Close in SNR: 156 dBc/Hz, 1 kHz oset, 3 dBFS Digital demodulator/decimator I/Q demodulator with programmable oscillator FIR decimation filter APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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AD9670 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CW Doppler Operation ............................................................. 33 Applications ....................................................................................... 1 Digital Demodulator/Decimator .................................................. 35 General Description ......................................................................... 1 Vector Profile .............................................................................. 35 Revision History ............................................................................... 2 RF Decimator .............................................................................. 36 Functional Block Diagram .............................................................. 3 Baseband Demodulator and Decimator.................................. 37 Specif icat ions ..................................................................................... 4 Digital Test Waveforms .............................................................. 38 AC Specifications .......................................................................... 4 Digital Block Power Saving Scheme ........................................ 38 Digital Specifications ................................................................... 7 Serial Port Interface (SPI) .............................................................. 39 Switching Specifications .............................................................. 8 Hardware Interface ..................................................................... 39 Timing Diagrams .......................................................................... 9 Memory Map .................................................................................. 41 Absolute Maximum Ratings .......................................................... 11 Reading the Memory Map Table .............................................. 41 Thermal Impedance ................................................................... 11 Reserved Locations .................................................................... 41 ESD Caution ................................................................................ 11 Default Values ............................................................................. 41 Pin Configuration and Function Descriptions ........................... 12 Logic Levels ................................................................................. 41 Typical Performance Characteristics ........................................... 15 Recommended Startup Sequence ............................................ 41 TGC Mode Characteristics ....................................................... 15 Memory Map Register Descriptions ........................................ 51 CW Doppler Mode Characteristics ......................................... 19 Outline Dimensions ....................................................................... 52 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 52 TGC Operation ........................................................................... 20 Analog Test Signal Generation ................................................. 33 REVISION HISTORY 2/16Revision A: Initial Version Rev. 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