Product Information

AD9814JR

AD9814JR electronic component of Analog Devices

Datasheet
Analog Devices Analog Front End - AFE 14-Bit 3CH CCD Signal Processor

Manufacturer: Analog Devices
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 1
Multiples : 1

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AD9814JR
Analog Devices

1 : USD 19.6696
5 : USD 19.0118
10 : USD 18.3326
25 : USD 17.4531
50 : USD 16.8168
100 : USD 16.731
250 : USD 16.731
500 : USD 16.3854
1000 : USD 15.7657
N/A

Obsolete
     
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RoHS - XON
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Supply Voltage - Min
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Pd - Power Dissipation
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Complete 14-Bit a CCD/CIS Signal Processor AD9814 FEATURES PRODUCT DESCRIPTION 14-Bit 10 MSPS A/D Converter The AD9814 is a complete analog signal processor for CCD No Missing Codes Guaranteed imaging applications. It features a 3-channel architecture de- 3-Channel Operation Up to 10 MSPS signed to sample and condition the outputs of trilinear color 1-Channel Operation Up to 7 MSPS CCD arrays. Each channel consists of an input clamp, Corre- Correlated Double Sampling lated Double Sampler (CDS), offset DAC and Programmable 1-6x Programmable Gain Gain Amplifier (PGA), multiplexed to a high performance 14- 6300 mV Programmable Offset bit A/D converter. Input Clamp Circuitry The CDS amplifiers may be disabled for use with sensors such Internal Voltage Reference as Contact Image Sensors (CIS) and CMOS active pixel sen- Multiplexed Byte-Wide Output (8+6 Format) sors, which do not require CDS. 3-Wire Serial Digital Interface The 14-bit digital output is multiplexed into an 8-bit output +3/+5 V Digital I/O Compatibility word that is accessed using two read cycles. The internal regis- 28-Lead SOIC Package ters are programmed through a 3-wire serial interface, and pro- Low Power CMOS: 330 mW (Typ) vide adjustment of the gain, offset, and operating mode. Power-Down Mode: <1 mW The AD9814 operates from a single +5 V power supply, typi- APPLICATIONS cally consumes 330 mW of power, and is packaged in a 28-lead Flatbed Document Scanners SOIC. Film Scanners Digital Color Copiers Multifunction Peripherals FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CML CAPT CAPB AVDD AVSS DRVDD DRVSS VINR CDS PGA AD9814 OEB BANDGAP 9-BIT REFERENCE DAC 14 14:8 8 3:1 14-BIT VING CDS PGA DOUT MUX MUX ADC 9-BIT CONFIGURATION DAC REGISTER MUX REGISTER VINB CDS PGA SCLK DIGITAL RED CONTROL SLOAD 6 INTERFACE 9-BIT GREEN GAIN DAC SDATA BLUE REGISTERS RED INPUT 9 CLAMP GREEN OFFSET BIAS OFFSET BLUE REGISTERS CDSCLK1 CDSCLK2 ADCCLK REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD9814SPECIFICATIONS ANALOG SPECIFICATIONS (T to T , AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f = 6 MHz, f = f = MIN MAX ADCCLK CDSCLK1 CDSCLK2 2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.) J-Grade K-Grade Parameter Min Typ Max Min Typ Max Units CONVERSION RATE 3-Channel Mode with CDS 6 10 6 10 MSPS 1-Channel Mode with CDS 6 7 6 7 MSPS ACCURACY (Entire Signal Path) ADC Resolution 14 14 Bits 1 Integral Nonlinearity (INL) +2.5/6.0 +2.5/6.0 11.0 LSB INL 10 MHz +4.0/7.0 +4.0/7.0 LSB Differential Nonlinearity (DNL) +0.6/0.5 +0.6/0.5 1.0 LSB DNL 10 MHz +0.8/0.6 +0.8/0.6 LSB No Missing Codes Guaranteed 13 14 Bits Offset Error 12 12 104 mV 2 Gain Error 2.2 2.2 5.3 % FSR ANALOG INPUTS 3 Input Signal Range 4.0 4.0 V p-p 3 Allowable Reset Transient 1.0 1.0 V 4 Input Limits AVSS 0.3 AVDD + 0.3 AVSS 0.3 AVDD + 0.3 V Input Capacitance 10 10 pF Input Bias Current 10 10 nA AMPLIFIERS PGA Gain at Minimum 1 1 V/V PGA Gain at Maximum 5.8 5.8 V/V PGA Resolution 64 64 Steps PGA Monotonicity Guaranteed Guaranteed Programmable Offset at Minimum 300 300 mV Programmable Offset at Maximum +300 +300 mV Programmable Offset Resolution 512 512 Steps Programmable Offset Monotonicity Guaranteed Guaranteed NOISE AND CROSSTALK Input Referred Noise PGA Min 130 130 m V rms Total Output Noise PGA Min 0.55 0.55 LSB rms Input Referred Noise PGA Max 84 84 m V rms Total Output Noise PGA Max 2.0 2.0 LSB rms Channel-Channel Crosstalk <1 <1 LSB POWER SUPPLY REJECTION AVDD = +5 V 0.25 V 0.07 0.07 0.3 % FSR Differential VREF ( +25 C) CAPT-CAPB (4 V Input Range) 2.0 1.9 2.0 2.1 V CAPT-CAPB (2 V Input Range) 1.0 0.94 1.0 1.06 V TEMPERATURE RANGE Operating 0 +70 0 +70 C Storage 65 +150 65 +150 C POWER SUPPLIES AVDD +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V DRVDD +3.0 +5.0 +5.25 +3.0 +5.0 +5.25 V Total Operating Current AVDD 64 64 80 mA DRVDD 1.8 1.8 10 mA Power-Down Mode Current 150 150 m A Power Dissipation 330 330 450 mW Power Dissipation 10 MHz 355 355 mW Power Dissipation (1-Channel Mode) 220 220 265 mW 2 REV. 0

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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