110 MSPS/140 MSPS Analog Interface for Flat Panel Displays AD9985A FEATURES FUNCTIONAL BLOCK DIAGRAM Variable analog input bandwidth control AUTO-CLAMP Variable SOGIN bandwidth control LEVEL ADJUST Automated clamping level adjustment 8 R A/D R IN CLAMP OUTA 140 MSPS maximum conversion rate 300 MHz analog bandwidth AUTO-CLAMP 0.5 V to 1.0 V analog input range LEVEL ADJUST 500 ps p-p PLL clock jitter at 110 MSPS 8 G CLAMP A/D 3.3 V power supply IN G OUTA Full sync processing AUTO-CLAMP Selectable input filtering LEVEL ADJUST Sync detect for hot plugging 8 Midscale clamping B CLAMP A/D B IN OUTA Power-down mode MIDSCV HSYNC Low power: 500 mW typical COAST DTACK SYNC 4:2:2 output format mode PROCESSING HSOUT CLAMP AND CLOCK VSOUT FILT GENERATION APPLICATIONS SOGOUT SOGIN RGB graphics processing REF REF BYPASS SCL LCD monitors and projectors SERIAL REGISTER AND SDA Plasma display panels POWER MANAGEMENT AD9985A A0 Scan converters Microdisplays Figure 1. Digital TVs GENERAL DESCRIPTION The AD9985A is a complete 8-bit, 140 MSPS, monolithic When the Coast signal is presented, the PLL maintains its analog interface optimized for capturing RGB graphics signals output frequency in the absence of Hsync. A sampling phase from personal computers and workstations. Its 140 MSPS adjustment is provided. Data, Hsync, and clock output phase encode rate capability and full power analog bandwidth of 300 relationships are maintained. The AD9985A also offers full sync MHz support resolutions up to SXGA (1280 1024 at 75 Hz). processing for composite sync and sync-on-green applications. The AD9985A includes a 140 MHz triple ADC with internal A clamp signal is generated internally or can be provided by the 1.25 V reference, a PLL, and programmable gain, offset, and user through the CLAMP input pin. This interface is fully clamp control. The user provides only a 3.3 V power supply, programmable via a 2-wire serial interface. analog input, and horizontal sync (Hsync) and Coast signals. Fabricated in an advanced CMOS process, the AD9985A is Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. provided in a space-saving 80-lead LQFP surface-mount The AD9985As on-chip PLL generates a pixel clock from the Pb-free plastic package, and is specified over the 40C to Hsync input. Pixel clock output frequencies range from 12 MHz +85C temperature range. to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. 05484-001AD9985A TABLE OF CONTENTS Specifications..................................................................................... 3 Hsync Timing ............................................................................. 15 Explanation of Test Levels........................................................... 6 Coast Timing .............................................................................. 16 Absolute Maximum Ratings............................................................ 7 2-Wire Serial Register Map ........................................................... 17 ESD Caution.................................................................................. 7 2-Wire Serial Control Register Detail Chip Identification... 19 Pin Configuration and Function Descriptions............................. 8 PLL Divider Control .................................................................. 19 Design Guide................................................................................... 11 Clock Generator Control .......................................................... 20 General Description................................................................... 11 Clamp Timing............................................................................. 20 Digital Inputs .............................................................................. 11 Hsync Pulse Width..................................................................... 20 Input Signal Handling................................................................ 11 Input Gain ................................................................................... 20 Hsync, Vsync Inputs .................................................................. 11 Input Offset ................................................................................. 21 Serial Control Port ..................................................................... 11 Mode Control 1 .......................................................................... 21 Output Signal Handling............................................................. 11 2-Wire Serial Control Port ............................................................ 26 Clamping ..................................................................................... 11 Data Transfer via Serial Interface............................................. 26 RGB Clamping........................................................................ 11 Sync Slicer.................................................................................... 28 YUV Clamping ....................................................................... 12 Sync Separator ............................................................................ 28 Gain and Offset Control............................................................ 12 PCB Layout Recommendations.................................................... 29 Auto Offset .............................................................................. 12 Analog Interface Inputs............................................................. 29 Sync-on-Green............................................................................ 13 Power Supply Bypassing............................................................ 29 Clock Generation ....................................................................... 13 PLL ............................................................................................... 29 12-Bit Divisor Register .......................................................... 14 Outputs (Both Data and Clocks).............................................. 30 2-Bit VCO Range Register .................................................... 14 Digital Inputs .............................................................................. 30 3-Bit Charge Pump Current Register .................................. 14 Voltage Reference ....................................................................... 30 5-Bit Phase Adjust Register................................................... 14 Outline Dimensions....................................................................... 31 Power Management.................................................................... 14 Ordering GuIde .......................................................................... 31 Timing.......................................................................................... 15 REVISION HISTORY 7/05Revision 0: Initial Version Rev. 0 Page 2 of 32