Ultralow Distortion Differential ADC Driver Data Sheet ADA4938-1/ADA4938-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS ADA4938-1 Extremely low harmonic distortion (HD) TOP VIEW 106 dBc HD2 10 MHz 82 dBc HD2 50 MHz 109 dBc HD3 10 MHz 82 dBc HD3 50 MHz FB 1 12 PD +IN 2 11 OUT Low input voltage noise: 2.6 nV/Hz IN 3 10 +OUT High speed +FB49 V OCM 3 dB bandwidth of 1000 MHz, G = +1 Slew rate: 4700 V/s 0.1 dB gain flatness to 150 MHz Fast overdrive recovery of 4 ns Figure 1. ADA4938-1 Functional Block Diagram 1 mV typical offset voltage ADA4938-2 TOP VIEW Externally adjustable gain Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage UT1 IN1 1 18 +O Wide supply voltage range: +5 V to 5 V 2 17 V +FB1 OCM1 Single or dual amplifier configuration available +V 3 16 V S1 S2 +V 4 15 V S1 S2 APPLICATIONS FB2 5 14 PD2 6 +IN2 13 OUT2 ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Figure 2. ADA4938-2 Functional Block Diagram Line drivers 50 G = +2, V = 5V p-p O, dm GENERAL DESCRIPTION G = +2, V = 3.2V p-p O, dm 60 G = +2, V = 2V p-p O, dm G = +2, V = 1V p-p O, dm The ADA4938-1/ADA4938-2 are low noise, ultralow distortion, 70 high speed differential amplifiers. It is an ideal choice for 80 driving high performance ADCs with resolutions up to 16 bits 90 from dc to 27 MHz, or up to 12 bits from dc to 74 MHz. The output common-mode voltage is adjustable over a wide range, 100 allowing the ADA4938-1/ADA4938-2 to match the input of the 110 ADC. The internal common-mode feedback loop also provides 120 exceptional output balance as well as suppression of even-order 130 harmonic distortion products. 1 10 100 FREQUENCY (MHz) Full differential and single-ended-to-differential gain configurations Figure 3. SFDR vs. Frequency and Output Voltage are easily realized with the ADA4938-1/ADA4938-2. A simple makes them well-suited for a wide variety of data acquisition and external feedback network of four resistors determines the signal processing applications. closed-loop gain of the amplifier. The ADA4938-1 (single amplifier) is available in a Pb-free, The ADA4938-1/ADA4938-2 are fabricated using the Analog Devices, Inc., proprietary third generation, high voltage XFCB 3 mm 3 mm, 16-lead LFCSP. The ADA4938-2 (dual amplifier) is available in a Pb-free, 4 mm 4 mm, 24-lead process, enabling it to achieve very low levels of distortion with LFCSP. The pinouts have been optimized to facilitate layout and an input voltage noise of only 2.6 nV/Hz. The low dc offset and minimize distortion. The devices are specified to operate over excellent dynamic performance of the ADA4938-1/ADA4938-2 the extended industrial temperature range of 40C to +85C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. SFDR (dBc) V +V S S +V V S S V +V S S V +V S S 06592-001 06592-202 06592-002 24 IN2 7 +IN1 5 16 +FB2 8 23 FB1 6 15 +V 22 S2 9 V S1 7 14 +V 21 V S2 10 S1 V 20 8 13 OCM2 11 PD1 19 OUT1 +OUT2 12ADA4938-1/ADA4938-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 Analyzing an Application Circuit ............................................ 19 General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 19 Functional Block Diagrams ............................................................. 1 Estimating the Output Noise Voltage ...................................... 19 Revision History ............................................................................... 2 The Impact of Mismatches in the Feedback Networks ......... 20 Specif icat ions ..................................................................................... 3 Calculating the Input Impedance of an Application Circuit ..... 20 Dual-Supply Operation ............................................................... 3 Input Common-Mode Voltage Range in Single-Supply Applications ................................................................................ 20 Single-Supply Operation ............................................................. 5 Terminating a Single-Ended Input .......................................... 21 Absolute Maximum Ratings ............................................................ 7 Setting the Output Common-Mode Voltage .......................... 21 Thermal Resistance ...................................................................... 7 Layout, Grounding, and Bypassing .............................................. 23 ESD Caution .................................................................................. 7 High Performance ADC Driving ................................................. 24 Pin Configurations and Function Descriptions ........................... 8 Outline Dimensions ....................................................................... 25 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 25 Test Circuts ...................................................................................... 17 Terminology .................................................................................... 18 Added Settling Time Parameter, Table 3 ........................................ 5 REVISION HISTORY Changes to Linear Output Current Parameter, Table 3 ................ 5 6/2016Rev. A to Rev. B Changes to Figure 5 and Figure 6 .................................................... 8 Changed CP-16-2 to CP-16-21, CP-24-1 to CP-24-10 .. Throughout Added EP Row to Table 7 and EP Row to Table 8 ........................ 8 Changed ADA4938-x to ADA4938-1/ADA4938-2 .. Throughout Changes to Figure 41 ...................................................................... 14 Changes to Figure 1 and Figure 2 ................................................... 1 Added New Figure 53, Renumbered Sequentially ..................... 16 Changes to Figure 5 and Figure 6 ................................................... 8 Changes to Table 9 .......................................................................... 19 Updated Outline Dimensions ....................................................... 25 Added Exposed Pad Notation to Outline Dimensions ............. 25 Changes to Ordering Guide .......................................................... 25 Changes to Ordering Guide .......................................................... 25 10/2009Rev. 0 to Rev. A 11/2007Revision 0: Initial Version Added Settling Time Parameter, Table 1 ....................................... 3 Changes to Linear Output Current Parameter, Table 1 ............... 3 Rev. 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