1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer Data Sheet ADCLK846 FEATURES FUNCTIONAL BLOCK DIAGRAM Selectable LVDS/CMOS outputs LVDS/CMOS ADCLK846 Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) OUT0 (OUT0A) OUT0 (OUT0B) 54 fs integrated jitter (12 kHz to 20 MHz) V 100 fs additive broadband jitter REF OUT1 (OUT1A) 2.0 ns propagation delay (LVDS) CLK OUT1 (OUT1B) 135 ps output rise/fall (LVDS) CLK CTRL A 65 ps output-to-output skew (LVDS) LVDS/CMOS Sleep mode OUT2 (OUT2A) Pin-programmable control OUT2 (OUT2B) 1.8 V power supply OUT3 (OUT3A) APPLICATIONS OUT3 (OUT3B) Low jitter clock distribution OUT4 (OUT4A) Clock and data signal restoration OUT4 (OUT4B) CTRL B Level translation SLEEP Wireless communications OUT5 (OUT5A) Wired communications OUT5 (OUT5B) Medical and industrial imaging ATE and high performance instrumentation Figure 1. GENERAL DESCRIPTION The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout The clock input accepts various types of single-ended and buffer optimized for low jitter and low power operation. Possible differential logic levels including LVPECL, LVDS, HSTL, CML, configurations range from 6 LVDS to 12 CMOS outputs, and CMOS. including combinations of LVDS and CMOS outputs. Two Table 8 provides interface options for each type of connection. control lines are used to determine whether fixed blocks of The SLEEP pin enables a sleep mode to power down the device. outputs are LVDS or CMOS outputs. This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of 40C to +85C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 07226-001ADCLK846 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Functional Description .................................................................. 11 Functional Block Diagram .............................................................. 1 Clock Inputs ................................................................................ 11 General Description ......................................................................... 1 AC-Coupled Applications ......................................................... 11 Revision History ............................................................................... 2 Clock Outputs ............................................................................. 12 Specifications ..................................................................................... 3 Control and Function Pins ........................................................ 12 Electrical Characteristics ............................................................. 3 Power Supply ............................................................................... 12 Timing Characteristics ................................................................ 4 Applications Information .............................................................. 13 Clock Characteristics ................................................................... 5 Using the ADCLK846 Outputs for ADC Clock Applications ................................................................................ 13 Logic and Power Characteristics ................................................ 5 LVDS Clock Distribution .......................................................... 13 Absolute Maximum Ratings ............................................................ 6 CMOS Clock Distribution ........................................................ 13 Determining Junction Temperature .......................................... 6 Input Termination Options ....................................................... 14 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 15 Thermal Performance .................................................................. 6 Ordering Guide .......................................................................... 15 Pin Configuration and Function Descriptions ............................. 7 REVISION HISTORY 9/2017Rev. B to Rev. C 6/2009Rev. 0 to Rev. A Changes to Figure 2 .......................................................................... 7 No Content Updates ...................................................... Throughout Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 4/2009Revision 0: Initial Version 5/2010Rev. A to Rev. B Changes to Integrated Random Jitter Conditions ........................ 4 Rev. C Page 2 of 15