Product Information

ADP1050DC1-EVALZ

ADP1050DC1-EVALZ electronic component of Analog Devices

Datasheet
Power Management IC Development Tools daughter card ADP1050

Manufacturer: Analog Devices
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1: USD 162.2775 ea
Line Total: USD 162.28

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MOQ: 1  Multiples: 1
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Ships to you between Mon. 27 May to Fri. 31 May

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ADP1050DC1-EVALZ
Analog Devices

1 : USD 167.4291

0 - WHS 2


Ships to you between Fri. 31 May to Tue. 04 Jun

MOQ : 1
Multiples : 1

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ADP1050DC1-EVALZ
Analog Devices

1 : USD 160.6605

     
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Digital Controller for Isolated Power Supply with PMBus Interface Data Sheet ADP1050 FEATURES GENERAL DESCRIPTION Versatile digital voltage mode controller The ADP1050 is an advanced digital controller with a PMBus High speed input voltage feedforward control interface targeting high density, high efficiency dc-to-dc power 4 pulse-width modulation (PWM) logic outputs with 625 ps conversion. This controller implements voltage mode control resolution with high speed, input voltage feedforward operation for Switching frequency: 49 kHz to 625 kHz enhanced transient and noise performance. The ADP1050 has Frequency synchronization as slave device four programmable pulse-width modulation (PWM) outputs Pulse skipping power saving mode capable of controlling most high efficiency power supply Prebias startup topologies, with the added control of synchronous rectification (SR). Conditional overvoltage protection The ADP1050 implements several features to enable a robust Extensive fault detection and protection system of parallel and redundant operation for customers who PMBus compliant require high availability. The device provides synchronization, Graphical user interface (GUI) for ease of programming prebias startup, and conditional overvoltage techniques to On-board EEPROM for programming and data storage identify and safely shut down an erroneous power supply in Available in a 20-lead, 4 mm 4 mm LFCSP parallel operation mode. 40C to +125C operating temperature The ADP1050 is based on flexible state machine architecture APPLICATIONS and is programmed using an intuitive graphical user interface High density, isolated dc-to-dc power supplies (GUI). The easy to use GUI reduces design cycle time and Intermediate bus converters results in a robust, hardware coded system loaded into the built- High availability parallel power systems in EEPROM. The small size (4 mm 4 mm) of the LFCSP Server, storage, industrial, networking, and communications package makes the ADP1050 ideal for ultracompact, isolated infrastructure dc-to-dc power module or embedded power designs. TYPICAL APPLICATIONS CIRCUIT DC INPUT LOAD ADP3624 or ADP3654 SR1 SR2 VF OVP VS+ VS CS1 OUTA SYNI/FLGI ADuM3221 OUTB ADP1050 VDD RES ADD RTD VCORE PG/ALT CTRL SDA SCL AGND PMBus Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12039-006ADP1050 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PMBus Protection Commands ................................................. 30 Applications ....................................................................................... 1 Manufacturer Specific Protection Commands ....................... 32 General Description ......................................................................... 1 Manufacturer Specific Protection Responses ......................... 34 Typical Applications Circuit ............................................................ 1 Power Supply Calibration and Trim ............................................ 35 Revision History ............................................................................... 3 IIN Trim (CS1 Trim).................................................................... 35 Specifications ..................................................................................... 4 V Trim (VS Trim) ................................................................. 35 OUT Timing Diagram ........................................................................... 7 V Trim (VF Gain Trim) .......................................................... 35 IN Absolute Maximum Ratings ............................................................ 8 RTD and OTP Trim ................................................................... 36 Thermal Resistance ...................................................................... 8 Layout Guidelines ........................................................................... 37 Soldering ........................................................................................ 8 CS1 Pin ........................................................................................ 37 ESD Caution .................................................................................. 8 VS+ and VS Pins ...................................................................... 37 Pin Configuration and Function Descriptions ............................. 9 VDD Pin ...................................................................................... 37 Typical Performance Characteristics ........................................... 11 VCORE Pin ................................................................................. 37 Theory of Operation ...................................................................... 12 RES Pin ........................................................................................ 37 PWM Outputs (OUTA, OUTB, SR1, and SR2) ...................... 13 SDA and SCL Pins ...................................................................... 37 Synchronous Rectification ........................................................ 13 Exposed Pad ................................................................................ 37 PWM Modulation Limit and 180 Phase Shift ....................... 14 RTD Pin ....................................................................................... 37 Frequency Synchronization ...................................................... 14 AGND Pin ................................................................................... 37 2 Output Voltage Sense and Adjustment .................................... 16 PMBus/I C Communication ......................................................... 38 Digital Compensator .................................................................. 17 PMBus Features .......................................................................... 38 Closed-Loop Input Voltage Feedforward Control and Overview ..................................................................................... 38 VF Sense ...................................................................................... 18 2 PMBus/I C Address ................................................................... 38 Open-Loop Input Voltage Feedforward Operation ............... 19 Data Transfer............................................................................... 38 Open-Loop Operation ............................................................... 19 General Call Support ................................................................. 40 CS1 Current Sense (CS1 Pin) .................................................... 20 10-Bit Addressing ....................................................................... 40 Soft Start and Shutdown ............................................................ 20 Fast Mode .................................................................................... 40 Volt-Second Balance Control .................................................... 22 Fault Conditions ......................................................................... 40 Pulse Skipping ............................................................................. 23 Timeout Conditions ................................................................... 40 Prebias Startup ............................................................................ 23 Data Transmission Faults .......................................................... 40 VDD and VCORE ...................................................................... 23 Data Content Faults ................................................................... 41 Chip Password ............................................................................ 24 EEPROM ......................................................................................... 42 Power Monitoring, Flags, and Fault Responses .......................... 25 EEPROM Features ...................................................................... 42 Flags .............................................................................................. 25 EEPROM Overview ................................................................... 42 Voltage Readings ........................................................................ 28 EEPROM Password .................................................................... 42 Current Readings ........................................................................ 28 Page Erase Operation ................................................................. 42 Power Readings ........................................................................... 28 Read Operation (Byte Read and Block Read) ........................ 43 Duty Cycle Reading .................................................................... 28 Write Operation (Byte Write and Block Write) ..................... 43 Switching Frequency Reading .................................................. 28 Downloading EEPROM Settings to Internal Registers ......... 44 Temperature Reading ................................................................. 29 Saving Register Settings to the EEPROM ............................... 44 Temperature Linearization Scheme ......................................... 30 EEPROM CRC Checksum ........................................................ 44 Rev. A Page 2 of 92

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