50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO Data Sheet ADRF6806 FEATURES GENERAL DESCRIPTION IQ demodulator with integrated fractional-N PLL The ADRF6806 is a high dynamic range IQ demodulator with LO frequency range: 50 MHz to 525 MHz integrated PLL and VCO. The fractional-N PLL/synthesizer For the following specifications (LPEN = 0)/(LPEN = 1): generates a frequency in the range of 2.8 GHz to 4.2 GHz. A Input P1dB: 12.2 dBm/10.6 dBm programmable quadrature divider (divide ratio = 4 to 80) divides Input IP3: 28.5 dBm/25.2 dBm the output frequency of the VCO down to the required local Noise figure (DSB): 12.2/11.4 oscillator (LO) frequency to drive the mixers in quadrature. Voltage conversion gain: 1 dB/4.2 dB Additionally, an output divider (divide ratio = 4 to 8) generates Quadrature demodulation accuracy a divided-down VCO signal for external use. Phase accuracy: <0.5 The PLL reference input is supported from 10 MHz to 160 MHz. Amplitude accuracy: <0.1 dB The phase detector output controls a charge pump whose output Baseband demodulation: 135 MHz, 3 dB bandwidth is integrated in an off-chip loop filter. The loop filter output is SPI serial interface for PLL programming then applied to an integrated VCO. 40-lead, 6 mm 6 mm LFCSP The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential APPLICATIONS I and Q output paths have excellent quadrature accuracy and QAM/QPSK RF/IF demodulators can handle baseband signaling or complex IF up to 120 MHz. Cellular W-CDMA/CDMA/CDMA2000 A reduced power mode of operation is also provided by Microwave point-to-(multi)point radios programming the serial interface registers to reduce current Broadband wireless and WiMAX consumption, with slightly degraded input linearity and output current drive. The ADRF6806 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm 6 mm LFCSP package. Performance is specified over the 40C to +85C temperature range. FUNCTIONAL BLOCK DIAGRAM GND VCCLO VCCLO LOSEL IBBP IBBN GND 35 34 36 33 32 31 17 BUFFER 30 ADRF6806 GND CTRL DIV LON 37 29 DECL3 4, BUFFER 28 6, VCCRF 38 LOP 8 27 GND DIVIDER BUFFER FRACTION INTEGER MODULUS 2 11 MUX GND REG REG TO 12 40 DATA SPI 26 RFIN THIRD-ORDER QUAD CLK 13 INTERFACE FRACTIONAL 2 25 RFIP LE 14 INTERPOLATOR PRESCALER VCO GND 15 N COUNTER 2 CORE 2 24 GND REFIN 6 PHASE MUX + 23 CHARGE PUMP VOCM FREQUENCY 2 TEMP DETECTOR 250A, GND 7 SENSOR 22 VCCBB 500A (DEFAULT), 4 750A, 2.5V LDO VCO LDO 21 1000A GND MUXOUT 8 1 2 3 4 5 9 10 39 40 16 18 19 20 VCC1 VCC1 CPOUT GND RSET DECL2 VCC2 VTUNE DECL1 QBBP QBBN GND GND Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20102012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09335-001ADRF6806 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Structure....................................................................... 14 Applications....................................................................................... 1 LO Divider Programming......................................................... 21 General Description ......................................................................... 1 Programming Example.............................................................. 21 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 22 Revision History ............................................................................... 2 Basic Connections...................................................................... 22 Specifications..................................................................................... 3 Supply Connections ................................................................... 22 Timing Characteristics ................................................................ 5 Synthesizer Connections........................................................... 22 Absolute Maximum Ratings............................................................ 6 I/Q Output Connections ........................................................... 23 ESD Caution.................................................................................. 6 RF Input Connections ............................................................... 23 Pin Configuration and Function Descriptions............................. 7 Charge Pump/VTUNE Connections ...................................... 23 Typical Performance Characteristics ............................................. 9 LO Select Interface ..................................................................... 23 Synthesizer/PLL.......................................................................... 12 External LO Interface ................................................................ 23 Complementary Cumulative Distribution Functions (CCDF) Setting the Frequency of the PLL............................................. 23 ....................................................................................................... 13 Register Programming............................................................... 23 Circuit Description......................................................................... 14 EVM Measurements .................................................................. 24 LO Quadrature Drive................................................................. 14 Evaluation Board Layout and Thermal Grounding................... 25 V-to-I Converter......................................................................... 14 ADRF6806 Software .................................................................. 30 Mixers .......................................................................................... 14 Characterization Setups................................................................. 32 Emitter Follower Buffers ........................................................... 14 Outline Dimensions....................................................................... 36 Bias Circuitry .............................................................................. 14 Ordering Guide .......................................................................... 36 REVISION HISTORY 3/12Rev. A to Rev. B Changes to Phase NoiseUsing 67 kHz Loop Filter Parameter, Table 1 Added Phase NoiseUsing 2.5 kHz Loop Filter Parameter, Table 1 Added PLL Figure of Merit (FOM) Parameter, Table 1 ........................................................................ 4 Changes to Figure 21 and Figure 24 to Figure 26....................... 12 Changes to Figure 34...................................................................... 16 Changes to Figure 37...................................................................... 18 Changes to Figure 38...................................................................... 19 Changes to Figure 39...................................................................... 20 Changes to EVM Measurements Section and Figure 42, Deleted Figure 43 Renumbered Sequentially ........................ 24 Changes to Figure 43...................................................................... 25 Added Figure 44.............................................................................. 26 Changes to Figure 46 and Figure 47............................................. 27 Changes to Table 7.......................................................................... 29 Changes to Figure 48...................................................................... 30 Changes to Figure 49...................................................................... 31 6/11Rev. Sp0 to Rev. A Rev. B Page 2 of 36