a DSP Microcomputer ADSP-2181 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE PROGRAMMABLE 25 ns Instruction Cycle Time from 20 MHz Crystal POWER-DOWN I/O CONTROL 5.0 Volts FLAGS DATA ADDRESS MEMORY 40 MIPS Sustained Performance GENERATORS PROGRAM PROGRAM DATA SEQUENCER BYTE DMA Single-Cycle Instruction Execution MEMORY MEMORY DAG 1 DAG 2 CONTROLLER EXTERNAL Single-Cycle Context Switch ADDRESS BUS 3-Bus Architecture Allows Dual Operand Fetches in PROGRAM MEMORY ADDRESS Every Instruction Cycle DATA MEMORY ADDRESS EXTERNAL Multifunction Instructions DATA BUS PROGRAM MEMORY DATA Power-Down Mode Featuring Low CMOS Standby DATA MEMORY DATA Power Dissipation with 100 Cycle Recovery from Power-Down Condition DMA BUS INTERNAL ARITHMETIC UNITS SERIAL PORTS TIMER Low Power Dissipation in Idle Mode DMA SPORT 0 SPORT 1 PORT ALU MAC SHIFTER INTEGRATION ADSP-2100 BASE ADSP-2100 Family Code Compatible, with Instruction ARCHITECTURE Set Extensions 80K Bytes of On-Chip RAM, Configured as GENERAL DESCRIPTION 16K Words On-Chip Program Memory RAM The ADSP-2181 is a single-chip microcomputer optimized for 16K Words On-Chip Data Memory RAM digital signal processing (DSP) and other high speed numeric Dual Purpose Program Memory for Both Instruction processing applications. and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel The ADSP-2181 combines the ADSP-2100 family base archi- Shifter Computational Units tecture (three computational units, data address generators and Two Independent Data Address Generators a program sequencer) with two serial ports, a 16-bit internal Powerful Program Sequencer Provides DMA port, a byte DMA port, a programmable timer, Flag I/O, Zero Overhead Looping extensive interrupt capabilities, and on-chip program and data Conditional Instruction Execution memory. Programmable 16-Bit Interval Timer with Prescaler The ADSP-2181 integrates 80K bytes of on-chip memory con- 128-Lead TQFP/128-Lead PQFP figured as 16K words (24-bit) of program RAM, and 16K words SYSTEM INTERFACE (16-bit) of data RAM. Power-down circuitry is also provided to 16-Bit Internal DMA Port for High Speed Access to meet the low power needs of battery operated portable equip- On-Chip Memory ment. The ADSP-2181 is available in 128-lead TQFP and 128- 4 MByte Memory Interface for Storage of Data Tables lead PQFP packages. and Program Overlays 8-Bit DMA to Byte Memory for Transparent In addition, the ADSP-2181 supports new instructions, which Program and Data Memory Transfers include bit manipulationsbit set, bit clear, bit toggle, bit test I/O Memory Interface with 2048 Locations Supports new ALU constants, new multiplication instruction (x squared), Parallel Peripherals biased rounding, result free ALU operations, I/O memory trans- Programmable Memory Strobe and Separate I/O Memory fers and global interrupt masking for increased flexibility. Space Permits Glueless System Design Fabricated in a high speed, double metal, low power, CMOS Programmable Wait State Generation process, the ADSP-2181 operates with a 25 ns instruction cycle Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering time. Every instruction can execute in a single processor cycle. Automatic Booting of On-Chip Program Memory from The ADSP-2181s flexible architecture and comprehensive Byte-Wide External Memory, e.g., EPROM, or instruction set allow the processor to perform multiple opera- Through Internal DMA Port tions in parallel. In one processor cycle the ADSP-2181 can: Six External Interrupts Generate the next program address 13 Programmable Flag Pins Provide Flexible System Signaling Fetch the next instruction ICE-Port Emulator Interface Supports Debugging Perform one or two data moves in Final Systems Update one or two data address pointers ICE-Port is a trademark of Analog Devices, Inc. Perform a computational operation REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADSP-2181 This takes place while the processor continues to: Additional Information This data sheet provides a general overview of ADSP-2181 Receive and transmit data through the two serial ports functionality. For additional information on the architecture and Receive and/or transmit data through the internal DMA port instruction set of the processor, refer to the ADSP-2100 Family Receive and/or transmit data through the byte DMA port Users Manual, Third Edition. For more information about the Decrement timer development tools, refer to the ADSP-2100 Family Development Development System Tools Data Sheet. The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, ARCHITECTURE OVERVIEW supports the ADSP-2181. The System Builder provides a high The ADSP-2181 instruction set provides flexible data moves level method for defining the architecture of systems under and multifunction (one or two data moves with a computation) development. The Assembler has an algebraic syntax that is easy instructions. Every instruction can be executed in a single pro- to program and debug. The Linker combines object files into cessor cycle. The ADSP-2181 assembly language uses an alge- an executable file. The Simulator provides an interactive braic syntax for ease of coding and readability. A comprehensive instruction-level simulation with a reconfigurable user interface set of development tools supports program development. to display different portions of the hardware environment. A Figure 1 is an overall block diagram of the ADSP-2181. The PROM Splitter generates PROM programmer compatible files. processor contains three independent computational units: the The C Compiler, based on the Free Software Foundations ALU, the multiplier/accumulator (MAC) and the shifter. The GNU C Compiler, generates ADSP-2181 assembly source computational units process 16-bit data directly and have provi- code. The source code debugger allows programs to be cor- sions to support multiprecision computations. The ALU per- rected in the C environment. The Runtime Library includes over forms a standard set of arithmetic and logic operations division 100 ANSI-standard mathematical and DSP-specific functions. primitives are also supported. The MAC performs single-cycle The EZ-KIT Lite is a hardware/software kit offering a complete multiply, multiply/add and multiply/subtract operations with development environment for the entire ADSP-21xx family: an 40 bits of accumulation. The shifter performs logical and arith- ADSP-2181 evaluation board with PC monitor software plus metic shifts, normalization, denormalization and derive expo- Assembler, Linker, Simulator, and PROM Splitter software. nent operations. The shifter can be used to efficiently implement The ADSP-218x EZ-KIT Lite is a low-cost, easy to use hard- numeric format control including multiword and block floating- ware platform on which you can quickly get started with your point representations. DSP software design. The EZ-KIT Lite includes the following The internal result (R) bus connects the computational units so features: that the output of any unit may be the input of any unit on the 33 MHz ADSP-2181 next cycle. Full 16-bit Stereo Audio I/O with AD1847 SoundPort Codec A powerful program sequencer and two dedicated data address RS-232 Interface to PC with Windows 3.1 Control Software generators ensure efficient delivery of operands to these computa- Stand-Alone Operation with Socketed EPROM tional units. The sequencer supports conditional jumps, subroutine EZ-ICE Connector for Emulator Control calls and returns in a single cycle. With internal loop counters and DSP Demo Programs loop stacks, the ADSP-2181 executes looped code with zero over- The ADSP-218x EZ-ICE Emulator aids in the hardware debug- head no explicit jump instructions are required to maintain loops. ging of ADSP-218x systems. The emulator consists of hard- Two data address generators (DAGs) provide addresses for ware, host computer resident software and the target board simultaneous dual operand fetches (from data memory and connector. The ADSP-218x integrates on-chip emulation sup- program memory). Each DAG maintains and updates four port with a 14-pin ICE-Port interface. This interface provides a address pointers. Whenever the pointer is used to access data simpler target board connection requiring fewer mechanical (indirect addressing), it is post-modified by the value of one of clearance considerations than other ADSP-2100 Family EZ-ICEs. four possible modify registers. A length value may be associated The ADSP-218x device need not be removed from the target with each pointer to implement automatic modulo addressing system when using the EZ-ICE, nor are any adapters needed. Due for circular buffers. to the small footprint of the EZ-ICE connector, emulation can be Efficient data transfer is achieved with the use of five internal supported in final board designs. buses: The EZ-ICE performs a full range of functions, including: Program Memory Address (PMA) Bus In-target operation Program Memory Data (PMD) Bus Up to 20 breakpoints Data Memory Address (DMA) Bus Single-step or full-speed operation Data Memory Data (DMD) Bus Registers and memory values can be examined and altered Result (R) Bus PC upload and download functions The two address buses (PMA and DMA) share a single external Instruction-level emulation of program booting and execution address bus, allowing memory to be expanded off-chip, and the Complete assembly and disassembly of instructions two data buses (PMD and DMD) share a single external data C source-level debugging bus. Byte memory space and I/O memory space also share the See the Designing An EZ-ICE-Compatible Target System sec- external buses. tion of this data sheet for exact specifications of the EZ-ICE target Program memory can store both instructions and data, permit- board connector. ting the ADSP-2181 to fetch two operands in a single cycle, EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc. one from program memory and one from data memory. The REV. D 2