a DSP Microcomputer ADSP-2186 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE POWER-DOWN 25 ns Instruction Cycle Time 40 MIPS Sustained CONTROL FULL MEMORY MODE Performance MEMORY PROGRAMMABLE DATA ADDRESS I/O GENERATORS PROGRAM 8K 24 8K 16 EXTERNAL Single-Cycle Instruction Execution AND SEQUENCER PROGRAM DATA ADDRESS FLAGS DAG 1 DAG 2 MEMORY MEMORY BUS Single-Cycle Context Switch EXTERNAL 3-Bus Architecture Allows Dual Operand Fetches in DATA PROGRAM MEMORY ADDRESS BUS Every Instruction Cycle DATA MEMORY ADDRESS BYTE DMA Multifunction Instructions CONTROLLER PROGRAM MEMORY DATA Power-Down Mode Featuring Low CMOS Standby OR DATA MEMORY DATA Power Dissipation with 100 Cycle Recovery from EXTERNAL DATA Power-Down Condition BUS ARITHMETIC UNITS SERIAL PORTS TIMER Low Power Dissipation in Idle Mode INTERNAL ALU MAC SHIFTER SPORT 0 SPORT 1 DMA PORT INTEGRATION ADSP-2100 BASE HOST MODE ADSP-2100 Family Code Compatible, with Instruction ARCHITECTURE Set Extensions 40K Bytes of On-Chip RAM, Configured as Automatic Booting of On-Chip Program Memory from 8K Words On-Chip Program Memory RAM and Byte-Wide External Memory, e.g., EPROM, or 8K Words On-Chip Data Memory RAM Through Internal DMA Port Dual Purpose Program Memory for Both Instruction Six External Interrupts and Data Storage 13 Programmable Flag Pins Provide Flexible System Independent ALU, Multiplier/Accumulator and Barrel Signaling Shifter Computational Units UART Emulation through Software SPORT Reconfiguration Two Independent Data Address Generators ICE-Port Emulator Interface Supports Debugging Powerful Program Sequencer Provides in Final Systems Zero Overhead Looping Conditional Instruction Execution GENERAL DESCRIPTION Programmable 16-Bit Interval Timer with Prescaler The ADSP-2186 is a single-chip microcomputer optimized for 100-Lead LQFP and 144-Ball Mini-BGA digital signal processing (DSP) and other high speed numeric SYSTEM INTERFACE processing applications. 16-Bit Internal DMA Port for High Speed Access to The ADSP-2186 combines the ADSP-2100 family base archi- On-Chip Memory (Mode Selectable) tecture (three computational units, data address generators and 4 MByte Byte Memory Interface for Storage of Data a program sequencer) with two serial ports, a 16-bit internal Tables and Program Overlays DMA port, a byte DMA port, a programmable timer, Flag I/O, 8-Bit DMA to Byte Memory for Transparent Program extensive interrupt capabilities and on-chip program and data and Data Memory Transfers (Mode Selectable) memory. I/O Memory Interface with 2048 Locations Supports The ADSP-2186 integrates 40K bytes of on-chip memory con- Parallel Peripherals (Mode Selectable) figured as 8K words (24-bit) of program RAM and 8K words Programmable Memory Strobe and Separate I/O Memory (16-bit) of data RAM. Power-down circuitry is also provided to Space Permits Glueless System Design meet the low power needs of battery operated portable equip- (Mode Selectable) ment. The ADSP-2186 is available in 100-lead LQFP and Programmable Wait State Generation 144-Ball Mini-BGA packages. Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering In addition, the ADSP-2186 supports new instructions, which include bit manipulationsbit set, bit clear, bit toggle, bit test new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory trans- fers and global interrupt masking for increased flexibility. ICE-Port is a trademark of Analog Devices, Inc. All trademarks are the property of their respective holders. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADSP-2186 Fabricated in a high speed, double metal, low power, CMOS The EZ-ICE performs a full range of functions, including: process, the ADSP-2186 operates with a 25 ns instruction cycle In-target operation time. Every instruction can execute in a single processor cycle. Up to 20 breakpoints Single-step or full-speed operation The ADSP-2186s flexible architecture and comprehensive Registers and memory values can be examined and altered instruction set allow the processor to perform multiple opera- PC upload and download functions tions in parallel. In one processor cycle the ADSP-2186 can: Instruction-level emulation of program booting and execution Generate the next program address Complete assembly and disassembly of instructions Fetch the next instruction C source-level debugging Perform one or two data moves Update one or two data address pointers See Designing An EZ-ICE-Compatible Target System in the Perform a computational operation ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as well as the Target Board Connector for EZ-ICE Probe section This takes place while the processor continues to: of this data sheet, for the exact specifications of the EZ-ICE Receive and transmit data through the two serial ports target board connector. Receive and/or transmit data through the internal DMA port Receive and/or transmit data through the byte DMA port Additional Information Decrement timer This data sheet provides a general overview of ADSP-2186 functionality. For additional information on the architecture and Development System instruction set of the processor, refer to the ADSP-218x DSP The ADSP-2100 Family Development Software, a complete set Hardware Reference. For more information about the develop- of tools for software and hardware system development, sup- ment tools, refer to the ADSP-2100 Family Development Tools ports the ADSP-2186. The System Builder provides a high level Data Sheet. method for defining the architecture of systems under develop- ment. The Assembler has an algebraic syntax that is easy to ARCHITECTURE OVERVIEW program and debug. The Linker combines object files into an The ADSP-2186 instruction set provides flexible data moves executable file. The Simulator provides an interactive instruction- and multifunction (one or two data moves with a computation) level simulation with a reconfigurable user interface to display instructions. Every instruction can be executed in a single different portions of the hardware environment. A PROM processor cycle. The ADSP-2186 assembly language uses an Splitter generates PROM programmer compatible files. The algebraic syntax for ease of coding and readability. A compre- C Compiler, based on the Free Software Foundations GNU hensive set of development tools supports program development. C Compiler, generates ADSP-2186 assembly source code. The source code debugger allows programs to be corrected in POWER-DOWN the C environment. The Runtime Library includes over 100 CONTROL FULL MEMORY MODE ANSI-standard mathematical and DSP-specific functions. MEMORY PROGRAMMABLE DATA ADDRESS I/O GENERATORS PROGRAM 8K 24 8K 16 EXTERNAL AND The EZ-KIT Lite is a hardware/software kit offering a complete SEQUENCER PROGRAM DATA ADDRESS FLAGS DAG 2 DAG 1 MEMORY MEMORY BUS development environment for the ADSP-218x family: an ADSP- EXTERNAL DATA 218x-based evaluation board with PC monitor software plus PROGRAM MEMORY ADDRESS BUS Assembler, Linker, Simulator and PROM Splitter software. The DATA MEMORY ADDRESS BYTE DMA CONTROLLER ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware PROGRAM MEMORY DATA platform on which you can quickly get started with your DSP OR DATA MEMORY DATA software design. The EZ-KIT Lite includes the following features: EXTERNAL DATA BUS 75 MHz ADSP-2189M ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL Full 16-bit Stereo Audio I/O with AD73322 Codec ALU MAC SHIFTER SPORT 0 SPORT 1 DMA PORT RS-232 Interface ADSP-2100 BASE HOST MODE ARCHITECTURE EZ-ICE Connector for Emulator Control DSP Demo Programs Figure 1. Block Diagram Evaluation Suite of Visual DSP Figure 1 is an overall block diagram of the ADSP-2186. The The ADSP-218x EZ-ICE Emulator aids in the hardware debug- processor contains three independent computational units: the ging of an ADSP-2186 system. The emulator consists of hard- ALU, the multiplier/accumulator (MAC) and the shifter. The ware, host computer resident software, and the target board computational units process 16-bit data directly and have provi- connector. The ADSP-2186 integrates on-chip emulation sup- sions to support multiprecision computations. The ALU per- port with a 14-pin ICE-Port interface. This interface provides a forms a standard set of arithmetic and logic operations division simpler target board connection that requires fewer mechanical primitives are also supported. The MAC performs single-cycle clearance considerations than other ADSP-2100 Family EZ- multiply, multiply/add and multiply/subtract operations with ICEs. The ADSP-2186 device need not be removed from the 40 bits of accumulation. The shifter performs logical and arith- target system when using the EZ-ICE, nor are any adapters metic shifts, normalization, denormalization and derive expo- needed. Due to the small footprint of the EZ-ICE connector, nent operations. emulation can be supported in final board designs. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc. REV. B 2