a DSP Microcomputer ADSP-2191M PERFORMANCE FEATURES Multifunction Instructions 6.25 ns Instruction Cycle Time, for up to 160 MIPS Pipelined Architecture Supports Efficient Code Sustained Performance Execution ADSP-218x Family Code Compatible with the Same Architectural Enhancements for Compiled C and C++ Easy to Use Algebraic Syntax Code Efficiency Single-Cycle Instruction Execution Architectural Enhancements beyond ADSP-218x Family Single-Cycle Context Switch between Two Sets of Com- are Supported with Instruction Set Extensions for putation and Memory Instructions Added Registers, and Peripherals Instruction Cache Allows Dual Operand Fetches in Every Flexible Power Management with User-Selectable Instruction Cycle Power-Down and Idle Modes FUNCTIONAL BLOCK DIAGRAM INTERNALMEMORY FOUR INDEPENDENTBLOCKS ADSP-219x 24BIT JTAG ADDRESS DATA 6 DSPCORE 24 BIT ADDRESS DATA TEST & CACHE ADDRESS 16 BIT DATA EMULATION 64 24-BIT 16 BIT DATA ADDRESS DAG1 DAG2 PROGRAM 4 4 16 4 4 16 SEQUENCER EXTERNALPORT 24 PM ADDRESS BUS 22 I/OADDRESS 18 ADDR BUS DM ADDRESS BUS 24 MUX 24 DMA ADDRESS DMA 24 DMA DATA CONNECT 24 PMDATA BUS PX 16 DATA BUS MUX 16 DM DATA BUS 16 I/ODATA DATA REGISTER I/OPROCESSOR FILE 24 INPUT REGISTERS HOSTPORT I/OREGISTERS RESULT (MEMORY-MAPPED) 18 REGISTERS SERIAL PORTS BARREL CONTROL ALU MULT (3) 16 16-BIT SHIFTER DMA STATUS CONTROLLER 6 BUFFERS SPIPORTS (2) 2 UART PORT (1) 3 PROGRAMMABLE SYSTEM INTERRUPT CONTROLLER TIMERS (3) FLAGS (16) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel:781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax:781/326-8703 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices. BLOCK0 BLOCK1 BLOCK2 BLOCK3ADSP-2191M INTEGRATION FEATURES TABLE OF CONTENTS 160K Bytes On-Chip RAM Configured as 32K Words 24-Bit GENERAL DESCRIPTION .3 Memory RAM and 32K Words 16-Bit Memory RAM DSP Core Architecture 3 Dual-Purpose 24-Bit Memory for Both Instruction and DSP Peripherals Architecture .4 Data Storage Memory Architecture .5 Independent ALU, Multiplier/Accumulator, and Barrel Interrupts 6 Shifter Computational Units with Dual 40-Bit DMA Controller .7 Accumulators Host Port 7 Unified Memory Space Allows Flexible Address Genera- DSP Serial Ports (SPORTs) 8 tion, Using Two Independent DAG Units Serial Peripheral Interface (SPI) Ports .9 Powerful Program Sequencer Provides Zero-Overhead UART Port .9 Looping and Conditional Instruction Execution Programmable Flag (PFx) Pins 9 Enhanced Interrupt Controller Enables Programming of Low Power Operation 10 Interrupt Priorities and Nesting Modes Clock Signals 11 Reset .11 SYSTEM INTERFACE FEATURES Power Supplies .11 Host Port with DMA Capability for Glueless 8- or 16-Bit Booting Modes .11 Host Interface Bus Request and Bus Grant .12 16-Bit External Memory Interface for up to 16M Words of Instruction Set Description 13 Addressable Memory Space Development Tools 13 Three Full-Duplex Multichannel Serial Ports, with Additional Information .15 Support for H.100 and up to 128 TDM Channels with PIN FUNCTION DESCRIPTIONS 15 A-Law and -Law Companding Optimized for Telecom- munications Systems SPECIFICATIONS .18 Two SPI-Compatible Ports with DMA Support ABSOLUTE MAXIMUM RATINGS .19 UART Port with DMA Support ESD SENSITIVITY .19 16 General-Purpose I/O Pins with Integrated Interrupt Power Dissipation .19 Support TIMING SPECIFICATIONS .20 Three Programmable Interval Timers with PWM Output Drive Currents .40 Generation, PWM Capture/Pulsewidth Measurement, Power Dissipation .40 and External Event Counter Capabilities Test Conditions 40 Up to 11 DMA Channels Can Be Active at Any Given Time Environmental Conditions 41 for High I/O Throughput 144-Lead LQFP Pinout 43 On-Chip Boot ROM for Automatic Booting from External 144-Lead Mini-BGA Pinout .45 8- or 16-Bit Host Device, SPI ROM, or UART with OUTLINE DIMENSIONS .47 Autobaud Detection ORDERING GUIDE .48 Programmable PLL Supports 1 to 32 Input Frequency Revision History 48 Multiplication and Can Be Altered during Runtime IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 2.5 V Internal Operation and 3.3 V I/O 144-Lead LQFP and 144-Ball Mini-BGA Packages 2 REV. A