Mixed-Signal DSP Controller with CAN ADSP-21992 Dual 16-bit auxiliary PWM outputs FEATURES 16 general-purpose flag I/O pins ADSP-2199x, 16-bit, fixed-point DSP core with up to 160 3 programmable 32-bit interval timers MIPS sustained performance SPI communications port with master or slave operation 48K words of on-chip RAM, as 32K words on-chip 24-bit pro- Synchronous serial communications port (SPORT) capable of gram RAM, and 16K words on-chip, 16-bit data RAM software UART emulation External memory interface Controller area network (CAN) module, fully compliant with Dedicated memory DMA controller for data/instruction V2.0B standard transfer between internal/external memory Integrated watchdog timer Programmable PLL and flexible clock generation circuitry Dedicated peripheral interrupt controller with software enables full-speed operation from low speed priority control input clocks Multiple boot modes IEEE JTAG Standard 1149.1 test access port supports on-chip Precision 1.0 V voltage reference emulation and system debugging Integrated power-on-reset (POR) generator 8-channel, 14-bit analog-to-digital converter system, with up to 20 MSPS sampling rate (at 160 MHz core clock rate) Flexible power management with selectable power-down and idle modes 3-phase 16-bit center based PWM generation unit with 12.5 ns resolution at 160 MHz core clock (CCLK) rate 2.5 V internal operation with 3.3 V I/O Dedicated 32-bit encoder interface unit with companion Operating temperature ranges of 40 C to +85 C and 40 C encoder event timer to +125 C CLOCK GENERATOR/PLL 16K 16 4K 24 32K 24 JTAG DMRAM PMROM PMRAM ADSP-219x TESTAND EMULATION DSP CORE ADDRESS EXTERNAL I/O DATA MEMORY BUS PMADDRESS/DATA INTERFACE (EMI) CONTROL DMADDRESS/DATA I/OREGISTERS CONTROLLERAREA MEMORY DMA SPI SPORT NETWORK(CAN) CONTROLLER PWM ENCODER TIMER0 ADC PIPELINE GENERATION INTERRUPT INTERFACE AUXILIARY CONTROL FLASHADC WATCHDOG TIMER1 FLAG CONTROLLER UNIT PWM UNIT I/O TIMER (ANDEET) (ICNTL) UNIT TIMER2 POR VREF Figure 1. Functional Block Diagram Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781.326.3113 2007 Analog Devices, Inc. All rights reserved.ADSP-21992 TABLE OF CONTENTS General Description ................................................. 3 Power Supplies ................................................... 14 DSP Core Architecture ........................................... 3 Booting Modes ................................................... 14 Memory Architecture ............................................ 5 Instruction Set Description .................................... 14 Bus Request and Bus Grant ..................................... 6 Development Tools .............................................. 15 DMA Controller ................................................... 7 Designing an Emulator-Compatible DSP Board .......... 16 DSP Peripherals Architecture .................................. 7 Additional Information ........................................ 16 Serial Peripheral Interface (SPI) Port ......................... 7 Pin Function Descriptions ........................................ 17 DSP Serial Port (SPORT) ........................................ 8 Specifications ........................................................ 20 Controller Area Network (CAN) Module ................... 9 Operating Conditions ........................................... 20 Analog-to-Digital Conversion System ........................ 9 Electrical Characteristics ....................................... 23 Voltage Reference ................................................. 9 Absolute Maximum Ratings ................................... 30 PWM Generation Unit ......................................... 10 ESD Caution ...................................................... 30 Auxiliary PWM Generation Unit ............................ 10 Timing Specifications ........................................... 30 Encoder Interface Unit ......................................... 10 Power Dissipation ............................................... 50 Flag I/O (FIO) Peripheral Unit ............................... 11 Test Conditions ..................................................... 51 Watchdog Timer ................................................ 11 Output Disable Time ............................................ 51 General-Purpose Timers ....................................... 11 Output Enable Time ............................................ 51 Interrupts ......................................................... 11 Example System Hold Time Calculation ................... 51 Peripheral Interrupt Controller .............................. 12 Pin Configurations ................................................. 52 Low Power Operation .......................................... 12 Outline Dimensions ................................................ 57 Clock Signals ..................................................... 13 Ordering Guide ..................................................... 59 Reset and Power-On Reset (POR) ........................... 13 REVISION HISTORY 8/07Rev. 0 to Rev. A Added RoHS part number to Ordering Guide ............... 59 Rev. A Page 2 of 60 August 2007