Blackfin Embedded Processor ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 support (ADSP-BF518/ADSP-BF518F only) Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats RISC-like register and instruction model for ease of programming and compiler-friendly support 2 dual-channel, full-duplex synchronous serial ports 2 (SPORTs), supporting 8 stereo I S channels Advanced debug, trace, and performance monitoring 12 peripheral DMAs, 2 mastered by the Ethernet MAC Wide range of operating voltages. See Operating Conditions on Page 22 2 memory-to-memory DMAs with external request lines Qualified for Automotive Applications. See Automotive Event handler with 56 interrupt inputs Products on Page 67 2 serial peripheral interfaces (SPI) 168-ball CSP BGA or 176-lead LQFP with exposed pad Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA MEMORY 2 UARTs with IrDA support 116K bytes of on-chip memory 2-wire interface (TWI) controller External memory controller with glueless support for SDRAM Eight 32-bit timers/counters with PWM support and asynchronous 8-bit and 16-bit memories 3-phase 16-bit center-based PWM unit Optional 4M bit SPI flash with boot option 32-bit general-purpose counter Flexible booting options from internal SPI flash, OTP Real-time clock (RTC) and watchdog timer memory, external SPI/parallel memories, or from SPI/UART 32-bit core timer host devices 40 general-purpose I/Os (GPIOs) Code security with Lockbox secure technology Debug/JTAG interface One-time-programmable (OTP) memory On-chip PLL capable of frequency multiplication Memory management unit providing memory protection RTC OTP WATCHDOG TIMER PERIPHERAL ACCESS BUS COUNTER JTAG TEST AND EMULATION 3-PHASE PWM TIMER70 TWI INTERRUPT B CONTROLLER SPORT1-0 RSI (SDIO) PORTS L1 L1 DMA INSTRUCTION DATA PPI CONTROLLER MEMORY MEMORY UART10 DMA EXTERNAL EMAC 16 DMA CORE BUS BUS EXTERNAL ACCESS BUS SPI1 BOOT EXTERNAL PORT SPI0 FLASH, SDRAM CONTROL ROM 4M bit SPI Flash (See Table 1) Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F TABLE OF CONTENTS Features ................................................................. 1 Signal Descriptions ................................................. 19 Memory ................................................................ 1 Specifications ........................................................ 22 Peripherals ............................................................. 1 Operating Conditions ........................................... 22 General Description ................................................. 3 Electrical Characteristics ....................................... 24 Portable Low Power Architecture ............................. 3 Flash Memory Characteristics ................................ 26 System Integration ................................................ 3 Absolute Maximum Ratings ................................... 27 Blackfin Processor Core .......................................... 3 Package Information ............................................ 28 Memory Architecture ............................................ 5 ESD Sensitivity ................................................... 28 Event Handling .................................................... 7 Timing Specifications ........................................... 29 DMA Controllers .................................................. 8 Output Drive Currents ......................................... 52 Processor Peripherals ............................................. 8 Test Conditions .................................................. 54 Dynamic Power Management ................................ 12 Thermal Characteristics ........................................ 58 Voltage Regulation Interface .................................. 14 176-Lead LQFP Lead Assignment ............................... 59 Clock Signals ..................................................... 14 168-Ball CSP BGA Ball Assignment ........................... 62 Booting Modes ................................................... 15 Outline Dimensions ................................................ 65 Instruction Set Description ................................... 16 Surface-Mount Design .......................................... 66 Development Tools ............................................. 16 Automotive Products .............................................. 67 Additional Information ........................................ 18 Ordering Guide ..................................................... 67 Related Signal Chains .......................................... 18 Lockbox Secure Technology Disclaimer ................... 18 REVISION HISTORY 5/13Rev. B to Rev. C Added Flash Memory Block Diagram ........................... 6 Added Internal Flash Memory Signal Descriptions ........... 7 Added footnote 1 to V parameter in DDOTP Operating Conditions ............................................. 22 Added footnote 7 in Operating Conditions .................. 22 Corrected transposed typical and maximum values for I DDFLASH1 parameter in Electrical Characteristics ........................ 24 Corrected several values in Dynamic Current in CCLK Domain (mA, with ASF = 1.0) .............................................. 26 Corrected typographical error of parameter name in External DMA Request Timing ................................. 34 Rev. C Page 2 of 68 May 2013