Blackfin a Embedded Processor ADSP-BF535 KEY FEATURES Memory Management Unit for Memory Protection 350 MHz High Performance Blackfin Processor Core Glueless External Memory Controllers Two 16-Bit MACs, Two 40-Bit ALUs, One 40-Bit Shifter, Synchronous SDRAM Support Four 8-Bit Video ALUs, and Two 40-Bit Accumulators Asynchronous with SRAM, Flash, ROM Support RISC-Like Register and Instruction Model for Ease of Programming and Compiler Friendly Support PERIPHERALS Advanced Debug, Trace, and Performance Monitoring 32-Bit, 33 MHz, 3.3 V, PCI 2.2 Compliant Bus Interface 1.0 V1.6 V Core V with Dynamic Power Management with Master and Slave Support DD 3.3 V I/O Integrated USB 1.1 Compliant Device Interface 260-Ball PBGA Package Two UARTs, One with IrDA Two SPI Compatible Ports MEMORY Two Full-Duplex Synchronous Serial Ports (SPORTs) 308K Bytes of On-Chip Memory: Four Timer/Counters, Three with PWM Support 16K Bytes of Instruction L1 SRAM/Cache Sixteen Bidirectional Programmable Flag I/O Pins 32K Bytes of Data L1 SRAM/Cache Watchdog Timer 4K Bytes of Scratch Pad L1 SRAM Real-Time Clock 256K Bytes of Full Speed, Low Latency L2 SRAM On-Chip PLL with 1 to 31 Frequency Multiplier Memory DMA Controller FUNCTIONAL BLOCK DIAGRAM JTAG TEST AND INTERRUPT WATCHDOG TIMER EMULATION CONTROLLER/ TIMER 32 REAL-TIME CLOCK B L1 L1 UART PORT 0 INSTRUCTION MMU DATA IrDA MEMORY MEMORY 256K BYTES L2 SRAM UART PORT 1 64 TIMER0, TIMER1, 32 SYSTEM BUS TIMER2 INTERFACE UNIT PROGRAMMABLE FLAGS 32 USB INTERFACE DMA CONTROLLER SERIAL PORTS (2) SPI PORTS (2) BOOT ROM 32 PCI BUS INTERFACE EXTERNAL PORT 32 FLASH SDRAM CONTROL Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. 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All rights reserved. owners OBSOLETEADSP-BF535 TABLE OF CONTENTS Programmable Flags Cycle Timing . 25 GENERAL DESCRIPTION 2 Timer PWM OUT Cycle Timing 26 Portable Low Power Architecture . 2 Asynchronous Memory Write Cycle Timing 27 System Integration . 2 Asynchronous Memory Read Cycle Timing . 28 ADSP-BF535 Peripherals . 3 SDRAM Interface Timing 29 Processor Core . 3 Serial Ports . 30 Memory Architecture 4 Serial Peripheral Interface (SPI) Port Internal (On-Chip) Memory 5 Master Timing . 32 External (Off-Chip) Memory . 5 Serial Peripheral Interface (SPI) Port PCI 5 Slave Timing . 33 I/O Memory Space . 5 Universal Asynchronous Receiver-Transmitter Booting . 6 (UART) PortReceive and Transmit Timing . 34 Event Handling . 6 JTAG Test and Emulation Port Timing 35 Core Event Controller (CEC) 6 Output Drive Currents 36 System Interrupt Controller (SIC) . 6 Power Dissipation 36 Event Control 7 Test Conditions 37 DMA Controllers . 7 Output Enable Time 37 External Memory Control . 8 Output Disable Time 37 PC133 SDRAM Controller 8 Example System Hold Time Calculation . 37 Asynchronous Controller 8 Environmental Conditions 38 PCI Interface . 8 260-Ball PBGA Pinout 39 PCI Host Function . 8 OUTLINE DIMENSIONS 44 PCI Target Function . 8 ORDERING GUIDE 44 USB Device 8 GENERAL DESCRIPTION Real-Time Clock 9 The ADSP-BF535 processor is a member of the Blackfin Watchdog Timer 9 processor family of products, incorporating the Micro Signal Timers 9 Architecture (MSA), jointly developed by Analog Devices, Inc. Serial Ports (Sports) . 9 and Intel Corporation. The architecture combines a dual MAC Serial Peripheral Interface (SPI) Ports . 10 state-of-the-art signal processing engine, the advantages of a UART Port . 10 clean, orthogonal RISC-like microprocessor instruction set, and Programmable Flags (PFX) . 11 Single-Instruction, Multiple Data (SIMD) multimedia capabili- Dynamic Power Management . 11 ties into a single instruction set architecture. Full On Operating Mode Maximum Performance . 11 By integrating a rich set of industry leading system peripherals Active Operating Mode and memory, Blackfin processors are the platform of choice for Moderate Power Savings 11 next generation applications that require RISC-like programma- Sleep Operating Mode bility, multimedia support, and leading edge signal processing in High Power Savings 11 one integrated package. Deep Sleep Operating Mode Portable Low Power Architecture Maximum Power Savings 12 Blackfin processors provide world class power management and Mode Transitions . 12 performance. Blackfin processors are designed in a low power Power Savings . 12 and low voltage design methodology and feature dynamic power Peripheral Power Control . 13 management, the ability to independently vary both the voltage Clock Signals 13 and frequency of operation to significantly lower overall power Booting Modes 14 consumption. Varying the voltage and frequency can result in a Instruction Set Description . 14 substantial reduction in power consumption, by comparison to Development Tools . 15 just varying the frequency of operation. This translates into EZ-KITLite forADSP-BF535 Blackfin Processor 16 longer battery life for portable appliances. Designing an Emulator Compatible Processor Board (Target) . 16 System Integration Additional Information 16 The ADSP-BF535 Blackfin processor is a highly integrated PIN DESCRIPTIONS 17 system-on-a-chip solution for the next generation of digital com- Unused Pins 20 munication and portable Internet appliances. By combining SPECIFICATIONS 21 industry-standard interfaces with a high performance signal ABSOLUTE MAXIMUM RATINGS 22 processing core, users can develop cost-effective solutions ESD SENSITIVITY 22 quickly without the need for costly external components. The TIMING SPECIFICATIONS 23 ADSP-BF535 Blackfin processor system peripherals include Clock and Reset Timing 24 UARTs, SPIs, SPORTs, general-purpose Timers, a Real-Time 2 REV. A OBSOLETE