Blackfin Embedded Processor ADSP-BF592 FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Four 32-bit timers/counters, three with PWM support Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 2 dual-channel, full-duplex synchronous serial ports (SPORT), 2 40-bit shifter supporting eight stereo I S channels RISC-like register and instruction model for ease of 2 serial peripheral interface (SPI) compatible ports programming and compiler-friendly support 1 UART with IrDA support Advanced debug, trace, and performance monitoring Parallel peripheral interface (PPI), supporting ITU-R 656 Accepts a wide range of supply voltages for internal and I/O video data formats operations, see Operating Conditions on Page 16 2-wire interface (TWI) controller Off-chip voltage regulator interface 9 peripheral DMAs 64-lead (9 mm 9 mm) LFCSP package 2 memory-to-memory DMA channels Event handler with 28 interrupt inputs MEMORY 32 general-purpose I/Os (GPIOs), with programmable 68K bytes of core-accessible memory hysteresis (See Table 1 on Page 3 for L1 and L3 memory size details) Debug/JTAG interface 64K byte L1 instruction ROM On-chip PLL capable of frequency multiplication Flexible booting options from internal L1 ROM and SPI mem- ory or from host devices including SPI, PPI, and UART Memory management unit providing memory protection WATCHDOG TIMER SPORT1 PORT F VOLTAGE REGULATOR INTERFACE JTAG TEST AND EMULATION SPI0 PERIPHERAL TIMER20 ACCESS BUS UART GPIO INTERRUPT CONTROLLER B PPI SPORT0 L1 INSTRUCTION L1 INSTRUCTION L1 DATA PORT G DMA ROM SRAM SRAM CONTROLLER DMA SPI1 ACCESS BUS DCB TWI DEB BOOT ROM Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Technical Support www.analog.comADSP-BF592 TABLE OF CONTENTS Features ................................................................. 1 Related Signal Chains ........................................... 13 Memory ................................................................ 1 Signal Descriptions ................................................. 14 Peripherals ............................................................. 1 Specifications ........................................................ 16 General Description ................................................. 3 Operating Conditions ........................................... 16 Portable Low Power Architecture ............................. 3 Electrical Characteristics ....................................... 18 System Integration ................................................ 3 Absolute Maximum Ratings ................................... 20 Blackfin Processor Core .......................................... 3 ESD Sensitivity ................................................... 20 Memory Architecture ............................................ 5 Package Information ............................................ 21 Event Handling .................................................... 5 Timing Specifications ........................................... 22 DMA Controllers .................................................. 6 Output Drive Currents ......................................... 36 Processor Peripherals ............................................. 6 Test Conditions .................................................. 37 Dynamic Power Management .................................. 8 Environmental Conditions .................................... 40 Voltage Regulation ................................................ 9 64-Lead LFCSP Lead Assignment ............................... 41 Clock Signals ....................................................... 9 Outline Dimensions ................................................ 43 Booting Modes ................................................... 11 Automotive Products .............................................. 44 Instruction Set Description ................................... 12 Ordering Guide ..................................................... 44 Development Tools ............................................. 12 Additional Information ........................................ 13 REVISION HISTORY 7/13Rev. A to Rev. B Corrected Processor Block Diagram ............................. 1 Updated Development Tools .................................... 12 Updated text in Signal Descriptions ............................ 14 Corrected V rating in Table 14, DDINT Absolute Maximum Ratings ..................................... 20 Rev. B Page 2 of 44 July 2013