TigerSHARC Embedded Processor a ADSP-TS202S 1149.1 IEEE-compliant JTAG test access port for on-chip KEY FEATURES emulation 500 MHz, 2.0 ns instruction cycle rate On-chip arbitration for glueless multiprocessing 12M bits of internalon-chipDRAM memory KEY BENEFITS 25 mm 25 mm (576-ball) thermally enhanced ball grid array package Provides high performance static superscalar DSP Dual-computation blockseach containing an ALU, a multi- operations, optimized for large, demanding multiproces- plier, a shifter, and a register file sor DSP applications Dual-integer ALUs, providing data addressing and pointer Performs exceptionally well on DSP algorithm and I/O manipulation benchmarks (see benchmarks in Table 1) Single-precision IEEE 32-bit and extended-precision 40-bit Supports low overhead DMA transfers between internal floating-point data formats and 8-, 16-, 32-, and 64-bit memory, external memory, memory-mapped peripherals, fixed-point data formats link ports, host processors, and other (multiprocessor) Integrated I/O includes 14-channel DMA controller, external DSPs port, four link ports, SDRAM controller, programmable Eases programming through extremely flexible instruction flag pins, two timers, and timer expired pin for system set and high-level-language-friendly DSP architecture integration Enables scalable multiprocessing systems with low communications overhead JTAGPORT DATAADDRESS GENERATION 12MBITSINTERNALMEMORY SOCBUS 6 32 32 INTEGER INTEGER MEMORY BLOCKS JTAG JALU KALU (PAGE CACHE) EXTERNAL 32-BIT 32-BIT 32-BIT 32-BIT 4CROSSBARCONNECT PROGRAM PORT SEQUENCER 32 A A A A D D D D ADDR 32 HOST J-BUSADDR ADDR FETCH 64 MULTI- DATA 128 J-BUS DATA PROC 8 SDRAM CTRL 32 K-BUSADDR CTRL 10 BTB C-BUS CTRL 128 K-BUSDATA ARB SOC 32 I-BUS ADDR EXT DMA I/F REQ 4 128 I-BUS DATA DMA PC LINKPORTS 21 S-BUS ADDR 4 8 IN L0 4 128 S-BUSDATA OUT 8 IAB T 4 8 IN L1 4 OUT 8 4 IN 8 L2 4 128 128 OUT 8 4 X Y IN 8 REGISTER REGISTER 128 128 L3 4 SHIFT ALU MUL MUL ALU SHIFT FILE FILE DAB DAB OUT 8 32-BIT 32-BIT 32-BIT 32-BIT COMPUTATIONAL BLOCKS Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.3113 2006 Analog Devices, Inc. All rights reserved. OBSOLETEADSP-TS202S TABLE OF CONTENTS General Description ................................................. 3 Output Enable Time ......................................... 38 Dual Compute Blocks ............................................ 4 Capacitive Loading ........................................... 38 Data Alignment Buffer (DAB) .................................. 4 Environmental Conditions .................................... 40 Dual Integer ALU (IALU) ....................................... 4 Thermal Characteristics ..................................... 40 Program Sequencer ............................................... 5 576-Ball BGA ED Pin Configurations ......................... 41 Interrupt Controller ........................................... 5 Outline Dimensions ................................................ 45 Flexible Instruction Set ........................................ 5 Surface Mount Design .......................................... 45 DSP Memory ....................................................... 5 Ordering Guide ..................................................... 46 External Port (Off-Chip Memory/Peripherals Interface) . 6 Host Interface ................................................... 6 Multiprocessor Interface ...................................... 7 REVISION HISTORY SDRAM Controller ............................................ 7 12/06Rev. B to Rev. C EPROM Interface .............................................. 7 Applied Corrections and Additional Information to: DMA Controller ................................................... 7 Figure 7, SCLK VREF Filtering Scheme .................... 10 Link Ports (LVDS) ................................................ 9 Operating Conditions ........................................... 21 Timer and General-Purpose I/O ............................... 9 Added On-Chip DRAM Refresh ............................. 27 Reset and Booting ................................................. 9 Ordering Guide .................................................. 46 Clock Domains .................................................... 9 Power Domains .................................................. 10 Filtering Reference Voltage and Clocks .................... 10 Development Tools ............................................. 10 Evaluation Kit .................................................... 11 Designing an Emulator-Compatible DSP Board (Target) .......................................... 11 Additional Information ........................................ 11 Pin Function Descriptions ....................................... 12 Strap Pin Function Descriptions ................................ 20 ADSP-TS202SSpecifications .................................. 21 Operating Conditions .......................................... 21 Electrical Characteristics ....................................... 22 Absolute Maximum Ratings .................................. 23 Package Information ........................................... 23 ESD Sensitivity ................................................... 23 Timing Specifications .......................................... 24 General AC Timing .......................................... 24 Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing ................ 30 Link PortData Out Timing ........................... 31 Link PortData In Timing ............................. 34 Output Drive Currents ......................................... 36 Test Conditions .................................................. 37 Output Disable Time ........................................ 37 Rev. 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