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ADV7343BSTZ

ADV7343BSTZ electronic component of Analog Devices

Datasheet
Video ICs Multiformat Encoder Six 11B 297MHz DAC

Manufacturer: Analog Devices
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1: USD 101.1253 ea
Line Total: USD 101.13

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ADV7343BSTZ
Analog Devices

1 : USD 101.1253
3 : USD 101.1253
5 : USD 97.9652
36 : USD 93.601
30 : USD 93.601
34 : USD 93.601

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ADV7343BSTZ
Analog Devices

1 : USD 26.9514
10 : USD 24.8598
25 : USD 22.8254
100 : USD 20.4144
250 : USD 19.4694
500 : USD 18.9969

     
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Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs Data Sheet ADV7342/ADV7343 FEATURES Enhanced definition(ED) programmable features (525p/625p) 74.25 MHz 16-/24-bit high definition input support 8 oversampling (216 MHz output) Compliant with SMPTE 274M (1080i), 296M (720p), Internal test pattern generator and 240M (1035i) Black bar, hatch, flat field/frame Six 11-bit, 297 MHz video DACs Individual Y and PrPb output delay 16 (216 MHz) DAC oversampling for SD Gamma correction 8 (216 MHz) DAC oversampling for ED Programmable adaptive filter control 4 (297 MHz) DAC oversampling for HD Fully programmable YCrCb to RGB matrix 37 mA maximum DAC output current Undershoot limiter NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support Macrovision Rev 1.2 (525p/625p) (ADV7342 only) NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) CGMS (525p/625p) and CGMS Type B (525p) Multiformat video input support Dual data rate (DDR) input support 4:2:2 YCrCb (SD, ED, and HD), 4:4:4 YCrCb (ED and HD), and Standard definition (SD) programmable features 4:4:4 RGB (SD, ED, and HD) 16 oversampling (216 MHz) Multiformat video output support Internal test pattern generator Composite (CVBS) and S-Video (Y-C) Color and black bar Component YPrPb (SD, ED, and HD) Controlled edge rates for start and end of active video Component RGB (SD, ED, and HD) Individual Y and PrPb output delay Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Undershoot limiter Simultaneous SD and ED/HD operation Gamma correction EIA/CEA-861B compliance support Digital noise reduction (DNR) Copy generation management system (CGMS) Multiple chroma and luma filters Closed captioning and wide screen signaling (WSS) Luma-SSAF filter with programmable gain/attenuation Integrated subcarrier locking to external video source PrPb SSAF Complete on-chip video timing generator Separate pedestal control on component and On-chip test pattern generation composite/S-Video output On-board voltage reference (optional external input) VCR FF/RW sync mode Programmable features Macrovision Rev 7.1.L1 (ADV7342 only) Luma and chroma filter responses Copy generation management system (CGMS) Vertical blanking interval (VBI) Wide screen signaling Subcarrier frequency (F ) and phase SC Closed captioning Luma delay 2 Serial MPU interface with I C compatibility High definition (HD) programmable features 3.3 V analog operation, 1.8 V digital operation, and 1.8 V or (720p/1080i/1035i) 3.3 V I/O operation 4 oversampling (297 MHz) Temperature range: 40C to +85C Internal test pattern generator Qualified for automotive applications Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control APPLICATIONS Programmable sharpness filter control DVD recorders and players CGMS (720p/1080i) and CGMS Type B (720p/1080i) High definition Blu-ray DVD players Undershoot limiter Dual data rate (DDR) input support Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20062015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADV7342/ADV7343 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SD Subcarrier Frequency Lock ................................................. 53 Applications ....................................................................................... 1 SD VCR FF/RW Sync ................................................................ 54 Revision History ............................................................................... 4 Vertical Blanking Interval ......................................................... 54 General Description ......................................................................... 5 SD Subcarrier Frequency Control ............................................ 54 Functional Block Diagram .............................................................. 6 SD Noninterlaced Mode ............................................................ 54 Specifications ..................................................................................... 7 SD Square Pixel Mode ............................................................... 55 Power Supply and Voltage Specifications .................................. 7 Filters ............................................................................................ 56 Voltage Reference Specifications ................................................ 7 ED/HD Test Pattern Color Controls ....................................... 57 Input Clock Specifications .......................................................... 7 Color Space Conversion Matrix ............................................... 57 Analog Output Specifications ..................................................... 8 SD Luma and Color Scale Control ........................................... 59 Digital Input/Output Specifications3.3 V ............................. 8 SD Hue Adjust Control .............................................................. 59 Digital Input/Output Specifications1.8 V ............................. 8 SD Brightness Detect ................................................................. 59 Digital Timing Specifications3.3 V ........................................ 9 SD Brightness Control ............................................................... 59 Digital Timing Specifications1.8 V ...................................... 10 SD Input Standard Autodetection ............................................ 60 MPU Port Timing Specifications ............................................. 11 Double Buffering ........................................................................ 61 Power Specifications .................................................................. 11 Programmable DAC Gain Control .......................................... 61 Video Performance Specifications ........................................... 12 Gamma Correction .................................................................... 61 Timing Diagrams ............................................................................ 13 ED/HD Sharpness Filter and Adaptive Filter Controls ......... 63 Absolute Maximum Ratings .......................................................... 20 ED/HD Sharpness Filter and Adaptive Filter Application Examples ...................................................................................... 64 Thermal Resistance .................................................................... 20 SD Digital Noise Reduction ...................................................... 65 ESD Caution ................................................................................ 20 SD Active Video Edge Control ................................................. 66 Pin Configuration and Function Descriptions ........................... 21 External Horizontal and Vertical Synchronization Control ... 68 Typical Performance Characteristics ........................................... 23 Low Power Mode ........................................................................ 69 MPU Port Description ................................................................... 28 2 Cable Detection .......................................................................... 69 I C Operation .............................................................................. 28 DAC Autopower-Down ............................................................. 69 Register Map Access ....................................................................... 30 Sleep Mode .................................................................................. 70 Register Programming ............................................................... 30 Pixel and Control Port Readback ............................................. 70 Subaddress Register (SR7 to SR0) ............................................ 30 Reset Mechanism........................................................................ 70 Input Configuration ....................................................................... 48 SD Teletext Insertion ................................................................. 70 Standard Definition Only .......................................................... 48 Printed Circuit Board Layout and Design .................................. 72 Enhanced Definition/High Definition Only .......................... 49 Unused Pins ................................................................................ 72 Simultaneous Standard Definition and Enhanced Definition/High Definition ....................................................... 49 DAC Configurations .................................................................. 72 Enhanced Definition Only (at 54 MHz) ................................. 50 Voltage Reference ....................................................................... 72 Output Configuration .................................................................... 51 Video Output Buffer and Optional Output Filter .................. 72 Design Features ............................................................................... 52 Printed Circuit Board (PCB) Layout ....................................... 73 Output Oversampling ................................................................ 52 Typical Application Circuit ....................................................... 75 Copy Generation Management System ....................................... 76 HD Interlace External P HSYNC and P VSYNC Considerations ............................................................................ 53 SD CGMS .................................................................................... 76 ED/HD Timing Reset ................................................................ 53 ED CGMS .................................................................................... 76 Rev. E Page 2 of 106

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8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

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