19-5633 Rev 11/10 DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES PIN ASSIGNMENT 10 years minimum data retention in the NC 1 32 V CC absence of external power A16 31 A15 2 A14 3 30 A17 Data is automatically protected during power 4 29 WE A12 loss A7 5 28 A13 Unlimited write cycles A6 6 27 A8 A5 7 26 A9 Low-power CMOS operation A4 8 25 A11 Read and write access times of 100ns A3 OE 9 24 Lithium energy source is electrically A2 10 23 A10 CE disconnected to retain freshness until power is A1 11 22 12 21 A0 DQ7 applied for the first time 13 20 DQ6 DQ0 Optional industrial (IND) temperature range 14 19 DQ1 DQ5 of -40C to +85C DQ2 15 18 DQ4 JEDEC standard 32-pin DIP package 16 17 GND DQ3 32-Pin Encapsulated Package 740mil Extended PIN DESCRIPTION A0A17 - Address Inputs DQ0DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V - Power (+3.3V) CC GND - Ground NC - No Connect DESCRIPTION The DS1249W 2048kb nonvolatile (NV) SRAMs are 2,097,152-bit, fully static, NV SRAMs organized as 262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors V for an out-of-tolerance condition. When such a condition occurs, the lithium CC energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit on the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing. 1 of 8 DS1249W READ MODE The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 18 address inputs OE (A A ) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight 0 17 data output drivers within t (Access Time) after the last address input signal is stable, providing that ACC CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either t for CO CE or t for OE rather than t . OE ACC WRITE MODE The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t ) WR before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE will disable the outputs in t from its falling edge. ODW DATA-RETENTION MODE The DS1249W provides full functional capability for V greater than 3.0 volts and write protects by CC 2.8V. Data is maintained in the absence of V without any additional support circuitry. The nonvolatile CC static RAMs constantly monitor V . Should the supply voltage decay, the NV SRAMs automatically CC write protects themselves, all inputs become dont care, and all outputs become high impedance. As V falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to CC RAM to retain data. During power-up, when V rises above approximately 2.5V, the power-switching CC circuit connects external V to the RAM and disconnects the lithium energy source. Normal RAM CC operation can resume after V exceeds 3.0V. CC FRESHNESS SEAL Each DS1249 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When V is first applied at a level greater than V , the lithium energy source is CC TP enabled for battery backup operation. 2 of 8