DS21448 3.3V E1/T1/J1 Quad Line Interface www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21448 is a quad-port E1 or T1 line interface Four Complete E1, T1, or J1 LIUs unit (LIU) for short-haul and long-haul applications. It Supports Long- and Short-Haul Trunks incorporates four independent transmitters and four Internal Software-Selectable Receive-Side independent receivers in a single 144-pin PBGA or Termination for 75/100/120 128-pin LQFP package. The transmit drivers 3.3V Power Supply generate the necessary G.703 E1 waveshapes in 32-Bit or 128-Bit Crystal-Less Jitter Attenuator 75 or 120 applications and the DSX-1 or CSU line Requires Only a 2.048MHz Master Clock for E1 build-outs of 0dB, -7.5dB, -15dB, and -22.5dB for T1 and T1, with the Option to Use 1.544MHz for T1 applications. Generates the Appropriate Line Build-Outs With and Without Return Loss for E1, and DSX-1 and APPLICATIONS CSU Line Build-Outs for T1 Integrated Multiservice Access Platforms AMI, HDB3, and B8ZS Encoding/Decoding T1/E1 Cross-Connects, Multiplexers, and Channel 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Banks Clock Output Synthesized to Recovered Clock Central-Office Switches and PBX Interfaces Programmable Monitor Mode for Receiver T1/E1 LAN/WAN Routers Loopbacks and PRBS Pattern Generation/ Wireless Base Stations Detection with Output for Received Errors Generates/Detects In-Band Loop Codes, 1 to 16 Bits, Including CSU Loop Codes ORDERING INFORMATION 8-Bit Parallel or Serial Interface with Optional PART* TEMP RANGE PIN-PACKAGE Hardware Mode DS21448 0C to +70C 144 TE-PBGA Muxed and Nonmuxed Parallel Bus Supports DS21448+ 0C to +70C 144 TE-PBGA Intel or Motorola DS21448N -40C to +85C 144 TE-PBGA Detects/Generates Blue (AIS) Alarms DS21448N+ -40C to +85C 144 TE-PBGA NRZ/Bipolar Interface for Tx/Rx Data I/O DS21448L 0C to +70C 128 LQFP Transmit Open-Circuit Detection DS21448L+ 0C to +70C 128 LQFP Receive Carrier Loss (RCL) Indication (G.775) DS21448LN -40C to +85C 128 LQFP High-Z State for TTIP and TRING DS21448LN+ -40C to +85C 128 LQFP 50mA Transmit Current Limiter RMS + Denotes lead-free/RoHS-compliant package. JTAG Boundary Scan Test Port per IEEE 1149.1 *All devices rated at 3.3V. Meets Latest E1 and T1 Specifications Including ANSI.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, TBR12, TBR13, and CTR4 Pin Configurations appear in Section 11. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 60 REV: 011206 DS21448 3.3V T1/E1/J1 Quad Line Interface TABLE OF CONTENTS 1. BLOCK DIAGRAMS ........................................................................................................................5 2. PIN DESCRIPTION ..........................................................................................................................7 3. DETAILED DESCRIPTION ............................................................................................................13 3.1 DS21448 AND DS21Q348 DIFFERENCES......................................................................................13 4. PORT OPERATION .......................................................................................................................14 4.1 HARDWARE MODE.........................................................................................................................14 4.2 SERIAL PORT OPERATION..............................................................................................................15 4.3 PARALLEL PORT OPERATION .........................................................................................................18 4.3.1 Device Power-Up and Reset................................................................................................................ 18 4.3.2 Register Map........................................................................................................................................ 18 4.3.3 Control Registers ................................................................................................................................. 19 5. STATUS REGISTERS....................................................................................................................23 6. DIAGNOSTICS ..............................................................................................................................28 6.1 IN-BAND LOOP-CODE GENERATION AND DETECTION......................................................................28 6.2 LOOPBACKS ..................................................................................................................................31 6.2.1 Remote Loopback (RLB) ..................................................................................................................... 31 6.2.2 Local Loopback (LLB) .......................................................................................................................... 31 6.2.3 Analog Loopback (LLB) ....................................................................................................................... 31 6.2.4 Dual Loopback (DLB)........................................................................................................................... 31 6.3 PRBS GENERATION AND DETECTION ............................................................................................31 6.4 ERROR COUNTER..........................................................................................................................31 6.5 ERROR COUNTER UPDATE ............................................................................................................32 6.6 ERROR INSERTION ........................................................................................................................32 7. ANALOG INTERFACE...................................................................................................................33 7.1 RECEIVER .....................................................................................................................................33 7.2 TRANSMITTER ...............................................................................................................................33 7.3 JITTER ATTENUATOR .....................................................................................................................34 7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................34 8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT..................................43 8.1 JTAG TAP CONTROLLER STATE MACHINE ....................................................................................43 8.2 INSTRUCTION REGISTER................................................................................................................45 8.3 TEST REGISTERS ..........................................................................................................................46 9. OPERATING PARAMETERS ........................................................................................................48 10. AC TIMING PARAMETERS AND DIAGRAMS..............................................................................49 11. PIN CONFIGURATIONS ................................................................................................................56 11.1 144-PIN BGA ............................................................................................................................56 11.2 128-PIN LQFP...........................................................................................................................57 12. PACKAGE INFORMATION ...........................................................................................................58 12.1 144-BALL TE-PBGA (56-G6020-001) .......................................................................................58 12.2 128-PIN LQFP (56-G4011-001)................................................................................................59 13. THERMAL INFORMATION............................................................................................................60 14. REVISION HISTORY......................................................................................................................60 2 of 60