DS2176Q+ Analog Devices

DS2176 T1 Receive Buffer www.dalsemi.com FEATURES PIN ASSIGNMENT Synchronizes looptimed and systemtimed T1 data streams SIGH 1 24 VDD RMSYN 23 SCKLSEL Twoframe buffer depth slips occur on frame 2 RCLK 3 22 SYCLK boundaries 4 21 SSER RSER Output indicates when slip occurs A SLIP 5 20 Buffer may be recentered externally B 6 19 SBIT8 C SMSYNC 7 18 Ideal for 1.544 to 2.048 MHz rate conversion D 8 17 SIGFRZ Interfaces to parallel or serial backplanes SCHCLK 9 16 SFSYNC Extracts and buffers robbedbit signaling SM0 10 15 ALN Inhibits signaling updates during alarm or slip SM1 FMS 11 14 12 13 VSS S/P conditions Integration feature debounces signaling 24-PIN 300 MIL DIP Slipcompensated output indicates when signaling updates occur Compatible with DS2180A T1 Transceiver Surface mount package available, designated DS2176Q Industrial temperature range of 40C to 4 3 2 1 28 27 26 5 25 A SSER +85C available, designated DS2176N 6 24 B SLIP 23 7 NC SBIT8 8 22 NC NC 9 21 C NC 20 10 D SMSYNC 11 19 SCHCLK SIGFRZ 12 13 14 15 16 17 18 28-PIN PLCC DESCRIPTION The DS2176 is a lowpower CMOS device specifically designed for synchronizing receive side loop timed Tcarrier data streams with system side timing. The device has several flexible operating modes which simplify interfacing incoming data to parallel and serial TDM backplanes. The device extracts, buffers and integrates ABCD signaling signaling updates are prohibited during alarm or slip conditions. The buffer replaces extensive hardware in existing applications with one skinny 24lead package. Application areas include digital trunks, drop and insert equipment, transcoders, digital crossconnects (DACS), private network equipment and PABXtocomputer interfaces such as DMI and CPI. 1 of 15 091599 SM0 RSER SM1 RCLK VSS RMSYNC S/P SIGH FMS VDD ALN SCKLSEL SFSYNC SYSCLKDS2176 DS2176 BLOCK DIAGRAM Figure 1 2 of 15