DS21Q354B+ Analog Devices

Preliminary Quad T1/E1 Transceiver (5V) DS21Q552/DS21Q554 Quad T1/E1 Transceiver (3.3V) DS21Q352/DS21Q354 P In One Small 27mm x 27mm Package Plus a Full Featured Framer with Alarm Detection/Generation, Each Multi-Chip Module (MCM) Contains Four Die of: to Allow the Same Footprint to Support T1 and E1 Applications 256lead MCM BGA package (27mm X 27mm) Tolerant Input & Outputs The Quad T1 and E1 Transceiver MCMs offer a high density packaging arrangement for the DS21352/DS21552 T1 Single-Chip Transceivers and the DS21354/DS21554 E1 Single-Chip Transceivers. Four silicon die of one of these devices is packaged in a Multi-Chip Module (MCM) with the electrical connections as shown in Figure 1. All of the functions available on the DS21352/DS21552 and DS21354/DS21554 are also available in the MCM packaged version however in order to minimize package This data sheet describes the electrical connections and the mechanical dimensions only. Please see the DS21352/DS21552 and DS21354/DS21554 data sheets for full details on all of the features and the operating characteristics of the device. December 29, 1998 , some signals have been deleted. These differences are detailed in Table 1. size DESCRIPTION Low Power 5V CMOS or Low Power 3.3V CMOS with 5V DS21Q352/DS21Q552 and DS21Q354/DS21Q554 are Pin Compatible IEEE 1149.1 JTAG-Boundary Scan Architecture 8.192MHz Backplane Data Stream All Four T1 or E1 Transceivers Can be Concatenated into a Single Data Sheets for Details on their Feature Set and Operation See the Specific DS21352/DS21552 and DS21354/DS21554 DS21Q554 5V E1 DS21Q354 3.3V E1 DS21Q552 5V T1 DS21Q352 3.3V T1 Device Supply Selection Guide: DS21554 (DS21Q554) DS21354 (DS21Q354) DS21552 (DS21Q552) DS21352 (DS21Q352) Channel Control and HDLC Controller Elastic Stores, Hardware Based Signaling Support, Per DS0 Each Transceiver Contains a Short & Long Haul Line Interface Four (4) Completely Independent T1 or E1 Transceivers FEATURES DALLAS SEMICONDUCTOR Table 1 1. The following signals are not available : XTALD / 8XCLK / TESO / TDATA / RCL / RDATA Schematic RPOSI TNEGO TCLKI LIUC TEST BTS 8 8 RFSYNC TDATA RTIP TCHCLK TLINK TLCLK TRING FMS DVDD RVDD 2 December 29, 1998 See Connecting Page TVDD TVSS RVSS DVSS TTIP RRING TCHBLK TCLK MCLK TSIG JTDO TSER JTDI TSYSCLK JTCLK TSSYNC JTMS TSYNC JTRST INT* TESO CS* D0/AD0 to D7/AD7 RMSYMC A0 to A7/ALE RSYNC RD* RSYSCLK WR* RSER MUX RSIG RSIGF RCHCLK RCHBLK RLCLK TNEGI RLINK TPOSI 8MCLK RLOS/LOTC RCLK TPOSO CI TCLKO XTALD / RDATA / RCL 8XCLK / Include: CO RNEGI & Left Open Circuited Signals Not Connected DS21354 / DS21554 RCLKI DS21352 / DS21552 / RNEGO SCT 1 RPOSO RCLKO Figure 1 DS21Q352 / DS21Q552 / DS21Q354 / DS21Q554 Configuration Changes from Normal DS21Q352/DS21Q552 & DS21Q354/DS21Q554 SEMICONDUCTOR DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet DALLAS