ABRIDGED DATA SHEET DS2432 1Kb Protected 1-Wire EEPROM with SHA-1 Engine FEATURES PIN CONFIGURATIONS 1128 Bits of 5V EEPROM Memory TOP VIEW Partitioned Into Four Pages of 256 Bits, a GND 1 6 NC 64-Bit Write-Only Secret, and Up to Five 1-Wire 2 5 NC General-Purpose Read/Write Registers NC 3 4 NC On-Chip 512-Bit ISO/IEC 10118-3 SHA-1 TSOC Engine to Compute 160-Bit Message (150 mils) Authentication Codes (MACs) and to Generate Secrets Write Access Requires Knowledge of the A1 MARK UCSP (TOP VIEW WITH LASER Secret and the Capability of Computing and MARK, CONTACTS NOT Transmitting a 160-Bit MAC Aas DS2432 VISIBLE) Authorization B yywwrr A2 = 1-WIRE Secret and Data Memory Can Be Write xx A3 = GND C ALL OTHER BUMPS: NC Protected (All or Page 0 Only) or Put in EPROM-Emulation Mode (Write to 0, 1 2 3 yywwr4 r = DATE/REVISION xx = LOT NUMBER Page 1) REFER TO THE PACKAGE RELIABILITY REPORT FOR Unique, Factory-Lasered and Tested 64-Bit IMPORTANT GUIDELINES ON QUALIFIED USAGE CONDITIONS. Registration Number Assures Absolute Traceability Because No Two Parts Are Alike Built-In Multidrop Controller Ensures Compatibility with Other 1-W ireNet ORDERING INFORMATION Products TEMP PIN- Reduces Control, Address, Data, and Power PART RANGE PACKAGE to a Single Data Pin DS2432P+ -40C to +85C 6 TSOC Directly Connects to a Single Port Pin of a DS2432P+T&R -40C to +85C 6 TSOC Microprocessor and Communicates at Up to 8 UCSP (2.5k DS2432X-S+ -40C to +85C 15.3kbps pcs, T&R) Overdrive Mode Boosts Communication +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. Speed to 90.9kbps Low-Cost 6-Lead TSOC Surface-Mount Request Full Data Sheet at: Package or Solder-Bumped UCSP Package www.maximintegrated.com/DS2432 Reads and Writes Over a Wide Voltage Range of 2.8V to 5.25V from -40C to +85C 1-Wire is a registered trademark and UCSP is a trademark of Maxim Integrated Products, Inc. 1 of 17 219-0003 Rev 9/12 ABRIDGED DATA SHEET DS2432 DESCRIPTION The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to five user read/write bytes, a 512-bit SHA-1 engine, and a fully-featured 1-Wire interface in a single chip. Each DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2432 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory, the register page or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a copy scratchpad command will transfer the data to its final memory location, provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the secret and additional data stored in the DS2432 including the devices registration number. Only a new secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute 160-bit message authentication codes (MAC) when reading a memory page or to compute a new secret, instead of loading it. Applications of the DS2432 include intellectual property security, after-market management of consumables, and tamper-proof data carriers. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2432. The DS2432 has five main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte pages of EEPROM, 4) 64-bit register page, 5) 64-bit Secrets Memory, and 6) a 512-bit SHA-1 Engine (SHA = Secure Hash Algorithm). The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first ovide pr one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive- Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at regular speed, the device will enter Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 9. After a ROM function command is successfully executed, the memory and SHA-1 functions become accessible and the master may provide any one of the seven memory function commands. The protocol * for these memory function commnds a is described in Figure . 7All data is read and written least significant bit first. * For Figure 7, refer to the full version of the data sheet. 2 of 17