ABRIDGED DATA SHEET Click here to ask an associate for production status of specific part numbers. DeepCover Secure Authenticator with DS28E35 1-Wire ECDSA and 1Kb User EEPROM General Description Features DeepCover embedded security solutions cloak sensitive ECDSA Engine for Public-Key Signature Using a data under multiple layers of advanced physical security Defined SEC Domain Parameter Set to provide the most secure key storage possible. On-Chip Hardware Random Number Generator The DeepCover Secure Authenticator (DS28E35) pro- Private and Public Key Can Be Computed by vides a highly secure solution for a host controller to the Device or Loaded from Outside with Optional authenticate peripherals based on the industry stan- Automatic Locking dard (FIPS 186) public-key based Elliptic Curve Digital Separate User-Programmable and Lockable Memory Signature Algorithm (ECDSA). The ECDSA engine com- Space to Store a Public-Key Certificate putes keys and signatures using a pseudorandom curve over a prime field according to the Standards for Efficient 17-Bit One-Time Settable, Nonvolatile Decrement- On-Command Counter Cryptography (SEC). The private and public key can be computed by the device or installed by the user and SHA-256 Engine to Compute a Hash of EEPROM optionally locked. Separate memory space is set aside to Page Data and Host Challenge for Subsequent store and lock a public-key certificate as it is needed to ECDSA Signing verify authenticity. In addition to ECDSA-related memory, 1024 Bit of User EEPROM Organized as Four Pages the device has 1024 bits of user memory that is organized of 256 Bits as four pages of 256 bits. Page protection modes include Programmable and Irreversible User EEPROM write protection, read protection, and one-time-program- Protection Modes Including Write Protection, Read mable (OTP) memory emulation modes. The DS28E35 Protection, and OTP/EPROM Emulation for Individual also features a one-time settable, nonvolatile 17-bit dec- Memory Pages rement-on-command counter, which can be used to keep track of the lifetime of the object to which the DS28E35 Unique Factory-Programmed 64-Bit Identification is attached. Each device has its own guaranteed unique Number 64-bit ROM identification number (ROM ID) that is fac- Single-Contact 1-Wire Interface Communicates with tory programmed into the chip. This unique ROM ID is Host at Up to 76.9kbps used as a fundamental input parameter for cryptographic Operating Range: 3.3V 10%, -40C to +85C operations and also serves as an electronic serial number within the application. The DS28E35 communicates over 8kV HBM ESD Protection (typ) for IO Pin the single-contact 1-Wire bus at overdrive speed. The 8-Pin TDFN and 6-Pin TSOC Packages communication follows the 1-Wire protocol with the ROM ID acting as node address in the case of a multi-device Typical Application Circuit 1-Wire network. 3.3V Applications R1 Authentication of Consuma bles 10k Peripheral Authentication V CC Medical Sensors PIOX Printer Cartridge Identificati on and Authentication Q1 R DS28E35 PUP BSS84 C 1-WIRE PIOY IO Ordering Information appears at end of data sheet. GND GND DeepCover and 1-Wire are registered trademarks of Maxim Integrated Products, Inc. 219-0028 Rev 6 11/21 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887 U.S.A. Tel: 781.329.4700 2021 Analog Devices, Inc. All rights reserved.ABRIDGED DATA SHEET DS28E35 DeepCover Secure Authenticator with 1-Wire ECDSA and 1Kb User EEPROM Absolute Maximum Ratings IO Voltage Range to GND ....................................-0.5V to +4.0V Storage Temperature Range .............................-55C to +125C IO Sink Current...................................................................20mA Lead Temperature (soldering, 10s) .................................+300C Operating Temperature Range ............................-40C to +85C Soldering Temperature (reflow) .......................................+260C Junction Temperature ......................................................+150C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TSOC TDFN Junction-to-Ambient Thermal Resistance ( ) .....126.7C/W Junction-to-Ambient Thermal Resistance ( ) ..........60C/W JA JA Junction-to-Case Thermal Resistance ( ) ...............37C/W Junction-to-Case Thermal Resistance ( ) ...............11C/W JC JC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (T = -40C to +85C.) (Note 2) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage V (Note 3) 2.97 3.63 V PUP 1-Wire Pullup Resistance R V = 3.3V 10% (Note 4) 300 1500 PUP PUP Input Capacitance C (Notes 5, 6) 1500 pF IO Input Load Current I IO pin at V 5 50 A L PUP High-to-Low Switching Threshold V (Notes 6, 7, 8) 0.65 x V V TL PUP Input Low Voltage V (Notes 3, 9) 0.3 V IL Low-to-High Switching Threshold V (Notes 6, 7, 10) 0.75 x V V TH PUP Switching Hysteresis V (Notes 6, 7, 11) 0.3 V HY Output Low Voltage V I = 4mA (Note 12) 0.4 V OL OL Recovery Time t R = 1500 (Notes 3, 13) 5 s REC PUP Time Slot Duration t (Notes 3, 14) 13 s SLOT IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE Reset Low Time t (Note 3) 48 80 s RSTL Reset High Time t (Note 15) 48 s RSTH Presence Detect Sample Time t (Notes 3, 16) 6 10 s MSP IO PIN: 1-Wire WRITE Write-Zero Low Time t (Notes 3, 17) 6 16 s W0L Write-One Low Time t (Notes 3, 17) 0.25 2 s W1L IO PIN: 1-Wire READ Read Low Time t (Notes 3, 18) 0.25 2 - d s RL Read Sample Time t (Notes 3, 18) t + d 2 s MSR RL www.analog.com Analog Devices 2